Wireless communications system with secondary synchronization code based on values in primary synchronization code

• US 7,103,085 B1
• Filed: 06/16/2000
• Issued: 09/05/2006
• Est. Priority Date: 06/18/1999
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sriram, Sundararajan, Dabak, Anand G., Hosur, Srinath
• Primary Examiner(s): Tran, Khai
• Assistant Examiner(s): CHANG, EDITH M
• Application Number:
  US09/595,561
• Time in Patent Office: 2,272 Days
• Field of Search: 375/130, 375/142, 375/343, 375/371, 375/145, 375/132, 375/149, 375/152, 375/134, 375/137, 375/140, 375/143, 375/148, 375/367, 370/342, 370/509, 370/320, 370/350, 370/514, 370/515, 370/335, 370/441, 370/479, 370/491, 380/34, 380/48, 380/9, 380/59
• US Class Current: 375/132
• CPC Class Codes: H04B 1/70735 Code identification H04B1/7083 takes precedence
• CPC Class Codes: H04B 1/7083 Cell search, e.g. using a three-step approach
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04J 13/12 Generation of orthogonal codes

Abstract

A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (50₁) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (50₂) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Claims

1. A wireless communication system, comprising:

a transmitter circuit comprising an encoder circuit for transmitting a plurality of frames;

wherein each of the plurality of frames comprises a primary synchronization code and a secondary synchronization code; and

wherein the encoder circuit comprises;

a circuit for providing the primary synchronization code in response to a first sequence; and

a circuit for providing the secondary synchronization code in response to a second sequence and a third sequence;

wherein the second sequence is selected from a plurality of sequences, wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences; and

wherein the third sequence comprises a sequence of bits from the first sequence, wherein the sequence of bits from the first sequence is consecutively repeated in the third sequence.

2. The system of claim 1 wherein the first sequence comprises a hierarchical sequence.

3. The system of claim 1 wherein the first sequence comprises a Golay sequence.

4. The system of claim 1:

wherein the second sequence comprises a plurality of code words; and

wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.

5. The system of claim 4 wherein the second sequence consists of fifteen of the code words.

6. The system of claim 5 wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences.

7. The system of claim 6:

wherein the 256 Walsh sequences have a defined order; and

wherein the plurality of Hadamard sequences comprise sixteen Hadamard sequences selected as every sixteenth sequence in the defined order.

8. The system of claim 6:

wherein the 256 Walsh sequences have a defined order; and

wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.

9. The system of claim 4 wherein the second sequence consists of sixteen of the code words.

10. The system of claim 9 the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences.

11. The system of claim 1 wherein the circuit for providing the secondary synchronization code comprises:

a circuit for performing an exclusive OR operation between the second sequence and the third sequence; and

a circuit for providing the secondary synchronization code in response to the exclusive OR operation.

12. The system of claim 1:

wherein the primary synchronization code comprises 8-bit values A and B and complements of the values A and B;

wherein the value A comprises a sequence A={1, 1, 1, 1, 1, 1, 1, −

1, −

1};

wherein the value B comprises a sequence B={1, −

1, 1, −

1, 1, −

1, −

1, 1}; and

wherein the primary synchronization code comprises a 256-bit sequence {A, B, A, B, A, B, −

A, −

B, −

A, −

B, A, B, −

A, −

B, −

A, −

B, A, B, A, B, A, B, −

, −

B, A, B, −

A, −

B, A, B, A, B}.

13. The system of claim 12:

wherein the second sequence comprises 256 bits; and

wherein the third sequence comprises 32 repeated instances of the value A.

14. The system of claim 13 wherein the circuit for providing the secondary synchronization code comprises:

a circuit for performing an exclusive OR operation between the second sequence and the third sequence; and

a circuit for providing the secondary synchronization code in response to the exclusive OR operation.

15. The system of claim 14:

wherein the second sequence comprises a plurality of code words; and

wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.

16. The system of claim 12:

wherein the second sequence comprises 256 bits;

wherein a complement of the value A is represented as −

A; and

wherein the third sequence comprises a 256-bit sequence {−

A, −

A, −

A, −

A, A, −

A, −

A, A, −

A, A, A, −

A, −

A, A, A, A, A, A, −

A, −

A, −

A, A, A, −

A, A, A, A, −

A, A, −

A, A, −

A}.

17. The system of claim 16 wherein the circuit for providing the secondary synchronization code comprises:

a circuit for performing an exclusive OR operation between the second sequence and the third sequence; and

a circuit for providing the secondary synchronization code in response to the exclusive OR operation.

18. The system of claim 17:

wherein the second sequence comprises a plurality of code words; and

wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.

19. The system of claim 18:

wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences;

wherein the 256 Walsh sequences have a defined order; and

wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.

20. The system of claim 1:

wherein the primary synchronization code consists of 8-bit values A and B and complements of the values A and B;

wherein the value A comprises a sequence A={1, 1, 1, 1, 1, −

1, −

1};

wherein the value B comprises a sequence B={1, −

1, 1, −

1, 1, −

1, −

1, 1};

wherein a value C is defined as a sequence C={A, −

B};

wherein the third sequence comprises a 256-bit sequence {C, C, C, −

C, C, C, −

C, −

C, C, −

C, C, −

C, −

C, −

C, −

C, −

C}.

21. The system of claim 20 wherein the circuit for providing the secondary synchronization code comprises:

a circuit for performing an exclusive OR operation between the second sequence and the third sequence; and

a circuit for providing the secondary synchronization code in response to the exclusive OR operation.

22. The system of claim 21:

wherein the second sequence comprises a plurality of code words; and

wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.

23. The system of claim 22:

wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences;

wherein the 256 Walsh sequences have a defined order; and

wherein the plurality of Hadamard sequences comprise sixteen Hadamard sequences selected as every sixteenth sequence in the defined order.

24. The system of claim 1 wherein the transmitter circuit comprises a CDMA transmitter.

25. The system of claim 1 wherein the circuit for providing the secondary synchronization code comprises a storage circuit for storing the secondary synchronization code.

26. The system of claim 25 wherein the secondary synchronization code stored by the storage circuit is derived from an exclusive OR operation between the second sequence and the third sequence.

27. A method of forming a primary synchronization code and a secondary synchronization code for communication in a plurality of frames in a wireless communication system, comprising the steps of:

providing the primary synchronization code in response to a first sequence; and

providing the secondary synchronization code in response to a second sequence and a third sequence; and

wherein the second sequence is selected from a plurality of sequences, wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences; and

wherein the third sequence comprises a sequence of bits from the first sequence, wherein the sequence of bits from the first sequence is consecutively repeated in the third sequence.

28. The method of claim 27 wherein the first sequence comprises a hierarchical sequence.

29. The method of claim 27 wherein the first sequence comprises a Golay sequence.

30. The method of claim 27:

wherein the second sequence comprises a plurality of code words; and

wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.

31. The method of claim 30 wherein the second sequence consists of fifteen of the code words.

32. The method of claim 31 wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences.

33. The method of claim 32:

wherein the 256 Walsh sequences have a defined order; and

wherein the plurality of Hadamard sequences comprise sixteen Hadamard sequences selected as every sixteenth sequence in the defined order.

34. The method of claim 30 wherein the second sequence consists of sixteen of the code words.

35. The method of claim 34:

wherein the 256 Walsh sequences have a defined order, and

wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.

36. The method of claim 27 wherein the step of providing the secondary synchronization code comprises:

performing an exclusive OR operation between the second sequence and the third sequence; and

providing the secondary synchronization code in response to the exclusive OR operation.

37. The method of claim 27:

wherein the primary synchronization code comprises 8-bit values A and B and complements of the values A and B;

wherein the value A comprises a sequence A={1, 1, 1, 1, 1, 1, −

1, −

1};

wherein the value B comprises a sequence B={1, −

1, 1, −

1, 1, −

1, −

1, 1}; and

wherein the primary synchronization code comprises a 256 bit sequence {A, B, A, B, A, B, −

A, −

B, −

A, −

B, A, B, −

A, −

B, −

A, −

B, A, B, A, B, A, B, −

A, −

B, A, B, −

A, −

B, A, B, A, B}.

38. The method of claim 37:

wherein the second sequence comprises 256 bits; and

wherein the third sequence comprises 32 repeated instances of the value A.

39. The method of claim 38 wherein the step of providing the secondary synchronization code comprises:

performing an exclusive OR operation between the second sequence and the third sequence; and

providing the secondary synchronization code in response to the exclusive OR operation.

40. The method of claim 39:

wherein the second sequence comprises a plurality of code words; and

wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.

41. The method of claim 37:

wherein the second sequence comprises 256 bits;

wherein a complement of the value A is represented as −

A; and

wherein the third sequence comprises a 256-bit sequence {−

A, −

A, −

A, −

A, A, −

A, −

A, A, −

A, A, A, −

A, −

A, A, A, A, A, A, −

A, −

A, −

A, A, A, −

A, A, A, A, −

A, A, −

A, A, −

A}.

42. The method of claim 41 wherein the step of providing the secondary synchronization code comprises:

performing an exclusive OR operation between the second sequence and the third sequence; and

providing the secondary synchronization code in response to the exclusive OR operation.

43. The method of claim 42:

wherein the second sequence comprises a plurality of code words; and

wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.

44. The method of claim 43:

wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences;

wherein the 256 Walsh sequences have a defined order; and

wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.

45. The method of claim 27:

wherein the primary synchronization code consists of 8-bit values A and B and complements of the values A and B;

wherein the value A comprises a sequence A{1, 1, 1, 1, 1, 1, −

1, −

1};

wherein the value B comprises a sequence B={1, −

1, 1, −

1, 1, −

1, −

1,

     1);

wherein a value C is defined as a sequence C={A, −

B};

wherein the third sequence comprises a 256-bit sequence {C, C, C, −

C, C, C, −

C, −

C, C, −

C, C, −

C, −

C, −

C, −

C, −

C}.

46. The method of claim 45 wherein the step of providing the secondary synchronization code comprises:

performing an exclusive OR operation between the second sequence and the third sequence; and

providing the secondary synchronization code in response to the exclusive OR operation.

47. The method of claim 46:

wherein the second sequence comprises a plurality of code words; and

wherein each of the plurality of code words is selected form a plurality of Hadamard sequences.

48. The method of claim 47:

wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences;

wherein the 256 Walsh sequences have a defined order, and

wherein the plurality of Hadamard sequences comprise sixteen Hadamard sequences selected as every sixteenth sequence in the defined order.

49. The method of claim 27 wherein the step of providing the secondary synchronization code comprises providing the secondary synchronization code from a storage circuit.

50. A method of encoding a synchronization code, comprising the steps of:

producing a primary synchronization code comprising a first code sequence;

producing a secondary synchronization code comprising a second code sequence combined with a third code sequence, wherein the second code sequence is from a plurality of sequences, wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences, and wherein the third code sequence comprises a sequence of bits of the first code sequence wherein the sequence of bits of the first code sequence is consecutively repeated in the third code sequence.

51. The method of claim 50 wherein the second code sequence comprises 256 bits, and wherein the third code sequence comprises 32 repeated instances of a subset of bits from the first code sequence.

52. The method of claim 51 wherein the step of producing the secondary synchronization code comprises performing an exclusive OR operation of the second code sequence with the third code sequence.

53. The method of claim 52 wherein the second code sequence comprises a plurality of code words, and wherein each code word of the plurality of code words is selected from a plurality of Hadamard sequences.

54. The method of claim 50 wherein each of the second and third code sequences comprise 256 bits, and wherein a subset of bits from the first code sequence comprises a fourth code sequence of bits and a complement of the fourth code sequence of bits.

55. The method of claim 54 wherein the step of producing the secondary synchronization code comprises performing an exclusive OR operation of the second code sequence with the third code sequence.

56. The method of claim 55 wherein the second code sequence comprises a plurality of code words, and wherein each code word of the plurality of code words is selected from a plurality of Hadamard sequences.

57. The method of claim 56 wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences, wherein the 256 Walsh sequences have a defined order, and wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.

58. A method of decoding a synchronization code, comprising the steps of:

identifying a primary synchronization code comprising a first code sequence;

identifying a secondary synchronization code comprising a second code sequence combined with a third code sequence, wherein the second code sequence is from a plurality of sequences, wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences, and wherein the third code sequence comprises a sequence of bits of the first code sequence, wherein the sequence of bits of the first code sequence is consecutively repeated in the third code sequence.

59. The method of claim 58 wherein the second code sequence comprises 256 bits, and wherein the third code sequence comprises 32 repeated instances of a subset of bits from the first code sequence.

60. The method of claim 59 wherein the second code sequence comprises a plurality of code words, and wherein each code word of the plurality of code words is selected from a plurality of Hadamard sequences.

61. The method of claim 58 wherein each of the second and third code sequences comprise 256 bits, and wherein a subset of bits from the first code sequence comprises a fourth code sequence of bits and a complement of the fourth code sequence of bits.

62. The method of claim 61 wherein the second code sequence comprises a plurality of code words, and wherein each code word of the plurality of code words is selected from a plurality of Hadamard sequences.

63. The method of claim 62 wherein the plurality of Hadamard sequences are selected form a set of 256 Walsh sequences, wherein the 256 Walsh sequences have a defined order, and wherein the plurality of Hadamard sequences comprise seventeen Hadamard sequences selected as every eighth sequence in the defined order.

64. A method of encoding a synchronization code, comprising the steps of:

producing a primary synchronization code comprising a first code sequence;

producing a secondary synchronization code comprising a second code sequence combined with a third code sequence, wherein the second code sequence is from a plurality of sequences, wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences, and wherein the third code sequence includes a plurality of subsets of bits, each subset including a fourth sequence of bits from the first code sequence and a complement of a fifth sequence of bits from the first code sequence.

65. The method of claim 64 wherein the step of producing the secondary synchronization code comprises performing an exclusive OR operation of the second code sequence with the third code sequence.

66. The method of claim 65 wherein the second code sequence comprises a plurality of code words, and wherein each of the plurality of code words is selected from a plurality of Hadamard sequences.

67. The method of claim 66 wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences, wherein the 256 Walsh sequences have a defined order, and wherein the plurality of Hadamard sequences comprise sixteen Hadamard sequences selected as every sixteenth sequence in the defined order.

68. The method of claim 67:

wherein the primary synchronization code consists of 8-bit values A and B and complements of the values A and B;

wherein the value A comprises a sequence A={1, 1, 1, 1, 1, 1, −

1, −

1};

wherein the value B comprises a sequence B={1, −

1, 1, −

1, 1, −

1, 1}

wherein a value C is defined as a sequence C {A, −

B};

wherein the third sequence comprises a 256-bit sequence {C, C, C, −

C, C, C, −

C, −

C, C, −

C, C, −

C, −

C, −

C, −

C, −

C}.

69. A method of decoding a synchronization code, comprising the steps of:

identifying a primary synchronization code comprising a first code sequence;

identifying a secondary synchronization code comprising a second code sequence combined with a third code sequence, wherein the second code sequence is from a plurality of sequences, wherein each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences, and wherein the third code sequence includes a plurality of subsets of bits, each subset including a fourth sequence of bits from the first code sequence and a complement of a fifth sequence of bits from the first code sequence.

70. The method of claim 69 wherein the second code sequence comprises a plurality of code words, and wherein, each of the plurality of code words is selected from a plurality of Hadamard sequences.

71. The method of claim 70 wherein the plurality of Hadamard sequences are selected from a set of 256 Walsh sequences, wherein the 256 Walsh sequences have a defined order, and wherein the plurality of Hadamard sequences comprise sixteen Hadamard sequences selected as every sixteenth sequence in the defined order.

72. The method of claim 71:

wherein the primary synchronization code consists of 8-bit values A and B and complements of the values A and B;

wherein the value A comprises a sequence A=1, 1, 1, 1, 1, −

1, −

1};

wherein the value B comprises a sequence B {1, −

1, 1, −

1, 1, −

1, −

1, 1};

wherein a value C is defined as a sequence C={A, −

B};

wherein the third sequence comprises a 256-bit sequence {C, C, C, −

C, C, C, −

C, −

C, C, −

C, C, −

C, −

C, C, −

C, −

C}.