Digital signal processor transceiver
First Claim
1. A method of selecting a frequency in a digital signal processor, comprising the steps of:
- inputting a series of data bits;
combining each data bit with at least one other data bit and with a series of counts from a counter that counts to a particular number, to generate said particular number of addresses for each data bit in said series of data bits;
using said addresses to determine a plurality of first values associated with each data bit and at least one previously inputted data bit;
successively adding the first values to a sum; and
on each successive adding of the first values of the sum, using at least a portion of the sum to provide an in-phase value and a quadrature value such that a phase integrated angle at each clock cycle may be produced.
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Accused Products
Abstract
A digital signal processor transceiver uses a finite impulse response filter memory to construct a phase integrated angle at each clock cycle. The FIR filter memory is addressed by a multibit pattern and a time count which are used in conjunction to determine the address. Each data word of the FIR filter memory represents the sum of two tap points multiplied by their tap coefficients. Several of the most significant bits of the phase integrated angle are used to address look up tables for the signal'"'"'s sine and cosine values. The address for the cosine look up table may further be phase compensated. Filter types other than a FIR filter may be used.
79 Citations
36 Claims
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1. A method of selecting a frequency in a digital signal processor, comprising the steps of:
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inputting a series of data bits; combining each data bit with at least one other data bit and with a series of counts from a counter that counts to a particular number, to generate said particular number of addresses for each data bit in said series of data bits; using said addresses to determine a plurality of first values associated with each data bit and at least one previously inputted data bit; successively adding the first values to a sum; and on each successive adding of the first values of the sum, using at least a portion of the sum to provide an in-phase value and a quadrature value such that a phase integrated angle at each clock cycle may be produced. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of selecting a frequency in a digital signal processor, comprising the steps of:
inputting a series of data bits; combining a plurality of said data bits with a series of counts from a counter that counts to a particular number, to generate said particular number of addresses for each bit in said series of inputted bits; using said addresses to determine a series of values from one or more taps in a finite impulse response filter in which each value of the series is individually and successively added to a sum; using at least a portion of the sum to determine an in-phase value and a quadrature value. - View Dependent Claims (11, 12, 13, 14)
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15. A method for selecting a frequency in a digital signal processor, comprising the steps of:
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inputting a series of bits; clocking a counter to yield a count value; and using a plurality of said bits and each count value of said counter as an address to determine a plurality of filter values for each bit in said series of bits. - View Dependent Claims (16, 17, 18)
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19. A method for selecting a frequency in a digital signal processor, comprising the steps of:
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inputting a series of bits; clocking a counter to yield a count value; using a plurality of said bits and the count value as an address to determine a plurality of filter values for each bit in said series, said filter values representing multiple taps of the filter; and using the most significant bits of said sum to derive a sine value, and further comprising using a phase correction process on the most significant bits and using a resulting output of the phase correction process to derive a cosine value. - View Dependent Claims (20)
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21. A digital signal processor transceiver, comprising:
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inputting a series of data bits; combining each data bit with at least one other data bit and with a series of counts from a counter that counts to a particular number to generate a series of addresses having said particular number of addresses for each data bit, means using said addresses for selecting a value representing two or more taps of a filter; means for phase integrating the value to provide a sum; and means for using a portion of the sum to determine an in-phase value and a quadrature value. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A digital signal processor transceiver, comprising:
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a latch for an address which includes data bits from a baseband and a count value from a counter, a first memory for providing an angle value corresponding to said address, an adder for phase integrating said angle value to form a sum, and a second memory containing sine values, a phase corrector, and a third memory contain cosine values, wherein the most significant bits from the sum address the second memory and are modified to provide an address for the third memory. - View Dependent Claims (36)
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Specification