Method and apparatus for representation of an address in canonical form

• US 7,103,751 B1
• Filed: 06/27/2002
• Issued: 09/05/2006
• Est. Priority Date: 06/27/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Miller, John Alan, Toll, Bret L., Fetterman, Michael A.
• Primary Examiner(s): Peugh, Brian R.
• Assistant Examiner(s): Farrokh, Hashem
• Application Number:
  US10/186,004
• Time in Patent Office: 1,531 Days
• Field of Search: 711205-214, 711/217, 711/220, 711202-203, 714 52- 53, 341 50-107, 712 2- 7, 712/24, 712/26, 712208-216, 712/226, 712/330
• US Class Current: 711/220
• CPC Class Codes: G06F 12/0615 Address space extension

Abstract

A method and apparatus for representing an address in canonical form. The address is received and an error indicator is computed according to whether the address is received in a correct canonical form. The error indicator is stored together with a portion of the address, the portion being less than the entire address. The error indicator, together with the portion of the address stored, represent the address received.

Claims

1. A method comprising:

receiving an address;

producing a first indicator with respect to a portion of the address when the address is received in a canonical form;

producing a second indicator with respect to the portion of the address when the address is received in a non-canonical form; and

storing the indicator produced, together with the portion of the address, to represent the address received.

2. The method of claim 1 wherein the portion of the address is less than the entire address.

3. The method of claim 1 wherein the address received comprises 64 bits.

4. The method of claim 3 wherein the portion of the address comprises 48 bits.

5. The method of claim 4 wherein the indicator is 1 bit.

6. An article of manufacture comprising

a machine-accessible medium including data that when accessed by a machine, cause the machine to perform the method of claim 5.

7. An apparatus comprising:

an address calculation unit to generate an M-bit compact representation of an N-bit address, M being less than N;

error checking logic coupled with the address calculation unit to indicate whether the N-bit address represented by the M-bit compact representation would be in a canonical form;

a fault generator to generate a fault when the error checking logic indicates that the N-bit address would be in a non-canonical form; and

address translation logic to receive the M-bit compact representation and to produce the corresponding N-bit address.

23. The apparatus of claim 7 wherein the error checking logic is also configurable to indicate whether the M-bit compact representation represents an N-bit address having a second canonical form different from the first canonical form.

24. The apparatus of claim 23 wherein an N-bit address having the second canonical form addresses any one of 2⁴⁸ storage locations.

25. The apparatus of claim 7 wherein N is equal to 64.

26. The apparatus of claim 25 wherein M is greater than 49.

27. The apparatus of claim 26 wherein M is equal to 50.

8. An apparatus comprising:

an address calculation unit to generate an M-bit compact representation of an N-bit address, M being less than N;

error checking logic coupled with the address calculation unit to indicate whether the M-bit compact representation represents an N-bit address having a first canonical form; and

address conversion logic to receive the M-bit compact representation and to produce the corresponding N-bit address.

9. The apparatus of claim 8 further comprising:

a fault generator to generate a fault when the error checking logic indicates that the N-bit address would not be in the first canonical form.

10. The apparatus of claim 8 wherein the error checking logic is also configurable to indicate whether the M-bit compact representation represents an N-bit address having a second canonical form different from the first canonical form.

11. The apparatus of claim 10 further comprising:

a fault generator to generate a fault responsive to an indication from the error checking logic that the N-bit address would not be in the first canonical form or responsive to an indication from the error checking logic that the N-bit address would not be in the second canonical form.

12. The apparatus of claim 10 wherein N is equal to 64.

13. The apparatus of claim 12 wherein M is greater than 49.

14. The apparatus of claim 13 wherein M is equal to 50.

15. The apparatus of claim 10 wherein an N-bit address having the second canonical form addresses any one of 2⁴⁸ storage locations.

16. An article of manufacture comprising:

a machine-accessible medium including data that, when accessed by the machine, cause the machine to;

receive a first M-bit compact representation of an N-bit address, M being less than N,

add an offset value to the first M-bit compact representation to generate a second M-bit compact representation; and

check if the second M-bit compact representation includes a valid indicator of a canonical N-bit address;

generate a canonical N-bit address from the second M-bit compact representation; and

access memory using the canonical N-bit address.

17. The article of manufacture of claim 16, the machine-accessible medium further including data that, when accessed by the machine, cause the machine to:

indicate whether the M-bit compact representation represents an N-bit address having a second canonical form different from the first canonical form.

18. The article of manufacture of claim 17, the machine-accessible medium further including data that when accessed by the machine, cause the machine to:

generate a fault responsive to an indication that the N-bit address would not be in the first canonical form or responsive to an indication that the N-bit address would not be in the second canonical form.

19. The article of manufacture of claim 18 wherein N is equal to 64.

20. The article of manufacture of claim 18 wherein M is greater than 49.

21. The article of manufacture of claim 20 wherein M is equal to 50.

22. The article of manufacture of claim 18 wherein an N-bit address having the second canonical form addresses any one of 2⁴⁸ storage locations.

28. An apparatus comprising:

receiving means for receiving an address;

checking means for producing a first indicator with respect to a portion of the address when the address is received in a canonical form and for producing a second indicator with respect to the portion of the address when the address is received in a non-canonical form; and

storage means for storing the indicator produced, together with the portion of the address, to represent the address received.

29. The apparatus of claim 28 wherein the portion of the address is less than the entire address.

30. The apparatus of claim 28 wherein the address received comprises 64 bits.

31. The apparatus of claim 30 wherein the portion of the address comprises 48 bits.

32. The apparatus of claim 31 wherein the indicator is 1 bit.