Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data

• US 7,103,790 B2
• Filed: 10/28/2003
• Issued: 09/05/2006
• Est. Priority Date: 04/07/2001
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Johnson, Leith L., Rentschler, Eric M., Hargis, Jeffrey G.
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US10/695,881
• Publication Number:
  US 20040088512A1
• Time in Patent Office: 1,043 Days
• Field of Search: 711/154, 711/167, 711/169, 711/105, 326/46, 326/93, 327/121, 327/122, 327/144, 327/152, 327/161, 365/193, 365/194, 365/233, 716/6, 713/401, 713/501
• US Class Current: 713/401
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M≧2).

Claims

1. Memory controller driver circuitry (FIG. 4, 400), comprising:

a data pad;

FIG. 4, DQ4);

N data propagation circuits (N≧

2) (FIG. 4, 402, 404);

a multiplexing stage (FIG. 4, 406) which provides data to at least N−

1 of the N data propagation circuits, said multiplexing stage enabling a coupling of a first data input stream (FIG. 4, 410) to each of the N data propagation circuits when the multiplexing stage is configured in a 1×

mode, and said multiplexing stage enabling a coupling of different data input streams (FIG. 4, 410, 412) to various of the N data propagation circuits when the multiplexing stage is configured in an M×

mode (1<

M≦

N); and

output merging circuitry (FIG. 4, 408) which alternately couples the N data propagation circuits to the data pad to thereby generate either a 1×

or M×

stream of data bits at the data pad.

2. Memory controller driver circuitry (FIG. 8, 800) as in claim 1, further comprising:

a strobe pad (FIG. 8, DQS18); and

means (FIG. 8, 824, 826, 828, 830, 832, 834) for producing at said strobe pad an M×

strobe signal which corresponds to said M×

data stream.

3. Memory controller driver circuitry as in claim 1, wherein said output merging circuitry comprises N sequentially clocked flip-flops (FIG. 8, 808, 810) which respectively receive and output data from the N data propagation circuits.

4. Memory controller driver circuitry as in claim 1, wherein said output merging circuitry comprises a multiplexer which receives and sequentially outputs data from the N data propagation circuits.

5. Memory controller driver circuitry as in claim 1, wherein said output merging circuitry comprises N tri-statable paths (FIG. 5, 504, 506) which respectively receive and sequentially output data from the N data propagation circuits.

6. Memory controller driver circuitry as in claim 5, wherein each of said N tri-statable paths comprises one of N sequentially clocked flip-flops (FIG. 5, 500, 502).

7. Memory controller driver circuitry as in claim 1, wherein N=M=2 (FIG. 4).

8. Memory controller driver circuitry as in claim 1, wherein a first of the N data propagation circuits is a simple wire route (FIG. 8, 802).

9. Memory controller driver circuitry as in claim 1, wherein said data pad is a bidirectional data pad.

10. A computer system (FIG. 1, 124), comprising:

a CPU (FIG. 1, 102);

a memory controller (FIG. 1, 100) coupled to said CPU;

an I/O controller (FIG. 1, 100) coupled to said CPU;

a number of I/O devices (FIG. 1, 112, 114, 116, 118, 120, 122) coupled to said I/O controller; and

a number of memory modules (FIG. 1, 104) coupled to said memory controller;

wherein said memory controller comprises a plurality of data pads (;

FIG. 4, DQ4) to which is coupled data driver circuitry (FIG. 4, 400) for driving data to said memory modules; and

wherein said data driver circuitry comprises, for each data pad;

i) N data propagation circuits (N≧

2) (FIG. 4, 402, 404);

ii) a multiplexing stage (FIG. 4, 406) which provides data to at least N−

1 of the N data propagation circuits, said multiplexing stage enabling a coupling of a first data input stream (FIG. 4, 410) to each of the N data propagation circuits when the multiplexing stage is configured in a 1×

mode, and said multiplexing stage enabling a coupling of different data input streams (FIG. 4, 410, 412) to various of the N data propagation circuits when the multiplexing stage is configured in an M×

mode (1<

M≦

N); and

iii) output merging circuitry (FIG. 4, 408) which alternately couples the N data propagation circuits to the data pad to thereby generate either a 1×

or M×

stream of data bits at the data pad.

11. A computer system as in claim 10, wherein the memory controller further comprises a plurality of strobe pads (FIG. 8, 800) to which is coupled strobe driver circuitry (FIG. 8, 824, 826, 828, 830, 832, 834) for driving strobes to said memory modules, said strobe driver circuitry comprising means for producing M×

strobe signals at said strobe pads.

12. A computer system as in claim 10, wherein for each data pad, said output merging circuitry comprises N tri-statable paths (FIG. 5, 504, 506) which respectively receive and sequentially output data from the N data propagation circuits.

13. A computer system as in claim 10, wherein N=M=2 (FIG. 4).

14. A computer system as in claim 10, wherein said memory controller and said I/O controller form an integrated memory and I/O controller (FIG. 1).