Memory system and controller for same
First Claim
1. A memory system comprising:
- first and second data memory components for storing data;
one parity memory component for storing parity information;
a first integrated circuit component directly coupled to the first and second data memory components; and
a second integrated circuit component directly coupled to the parity memory component and indirectly coupled to the first and second data memory components through the first integrated circuit, the first integrated circuit being indirectly coupled to the parity memory through the second integrated circuit;
wherein the first integrated circuit is configured to intercommunicate data with a host over a first portion of a system bus, the portion extending between the first integrated circuit and the host, the first and second integrated circuits further including reciprocally-configured logic to inter-communicate such that data communicated between the first integrated circuit and the host is capable of being communicated from the first integrated circuit to the second integrated circuit over a separate bus.
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Accused Products
Abstract
The present invention is broadly directed to a memory system comprising a a host integrated circuit component, at least two data memories, at least one parity memory for storing parity information corresponding to data stored in a corresponding address space of the data memories, and at least two controller integrated circuits. Each controller integrated circuit (IC) comprises memory control logic configurable to control communications between the controller IC and data memories directly connected to the controller IC, parity logic configurable to compute parity information for data communicated to or from the data memories, logic configurable to communicate the parity information to or from a companion IC, and logic configurable to communicated data to or from a companion IC.
33 Citations
16 Claims
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1. A memory system comprising:
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first and second data memory components for storing data; one parity memory component for storing parity information; a first integrated circuit component directly coupled to the first and second data memory components; and a second integrated circuit component directly coupled to the parity memory component and indirectly coupled to the first and second data memory components through the first integrated circuit, the first integrated circuit being indirectly coupled to the parity memory through the second integrated circuit; wherein the first integrated circuit is configured to intercommunicate data with a host over a first portion of a system bus, the portion extending between the first integrated circuit and the host, the first and second integrated circuits further including reciprocally-configured logic to inter-communicate such that data communicated between the first integrated circuit and the host is capable of being communicated from the first integrated circuit to the second integrated circuit over a separate bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory system comprising:
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a host integrated circuit component; at least two data memories; at least one parity memory for storing parity information corresponding to data stored in a corresponding address space of the data memories; at least two controller integrated circuits, each controller integrated circuit (IC) comprising memory control logic configurable to control communications between the controller IC and data memories directly connected to the controller IC, parity logic configurable to compute parity information for data communicated to or from the data memories, logic configurable to communicate the parity information to or from a companion IC, and logic configurable to communicated data to or from a companion IC. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. An integrated circuit component for performing memory control comprising:
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host communication logic capable of communicating with a host integrated circuit over only a portion of a system bus; data memory control logic configurable to control communications with directly connected data memory; and parity control logic configurable to compute parity information for data stored in associated data memory; intra-chip communication logic configurable to communicate data and/or parity information with a companion integrated circuit component over a dedicated communication link with the companion integrated circuit; wherein the data memory control logic, the parity control logic, and the intra-chip communication logic are capable of being configured in one configuration selected from the group consisting of; a) the data memory control logic is configured to communicate with directly-connected data memory and the parity control logic is configured to communicate parity information indirectly with a parity memory directly connected with a companion integrated circuit via the intra-chip communication logic; and b) the parity control logic is configured to compute parity information and communicate parity information with a directly-connected parity memory and the data control logic is configured to communicate indirectly with data memory directly connected with a companion integrated circuit via the intra-chip communication logic.
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Specification