Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system

• US 7,103,863 B2
• Filed: 06/10/2002
• Issued: 09/05/2006
• Est. Priority Date: 06/08/2001
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: Magma Design Automation (Synopsys Incorporated)
• Inventors: Burks, Timothy M., Swanson, Robert M., van Ginneken, Lukas, Riepe, Michael A., Vahtra, Karen F., Savoj, Hamid
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US10/167,293
• Publication Number:
  US 20040078767A1
• Time in Patent Office: 1,548 Days
• Field of Search: 716/7, 716/6, 716/8, 716/12, 716/2
• US Class Current: 716/113
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]

Abstract

A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block'"'"'s ancestors in the hierarchy.

Claims

1. A method used in producing a design of an integrated circuit said circuit design having cells and interconnects, said circuit having a representation that is hierarchically decomposed into a top-level and a plurality of blocks, at least some of the plurality of said blocks being capable of being further hierarchically decomposed and of having a parent block associated therewith, said method comprising:

processing at least one of said blocks such that an abstraction is created that includes physical interconnect information relating to interconnects between components within said at least one block, said physical interconnect information modeling parasitic electrical and physical effects of interconnects upon an estimated behavior of said integrated circuit, wherein said processing includes;

retaining only a sub-set of all of said physical interconnect information which influences physical and electrical behavior of said parent block; and

retaining only a sub-set of cells which influences a logical behavior of said parent block; and

utilizing said abstraction in another development phase performed on said parent block.

2. The method according to claim 1 wherein said utilizing includes:

replacing a description of said at least one block with a description of said abstraction.

3. The method according to claim 1, wherein retaining the sub-set of said physical interconnect information and of said cells includes:

determining contents of said at least one block'"'"'s netlist.

4. The method according to claim 3, wherein said contents of said at least one block'"'"'s netlist are determined by:

processing data inputs;

processing clock inputs.

5. The method according to claim 4 wherein processing data inputs comprises:

building a list of primary inputs.

6. The method according to claim 5 wherein until said list is empty, for each pin encountered, said processing data inputs further comprises:

removing said encountered pin from said list;

if said removed pin is a clock pin, then skipping said removed pin and continuing to the next pin; and

if said removed pin is not a clock pin, then processing forward said removed pin.

7. The method according to claim 6 wherein processing forward said removed pin comprises:

building a list of successors.

8. The method according to claim 7 wherein until said list of successors is empty, for each pin encountered, said processing forward said removed pin further comprises:

removing an encountered successor pin from said list of successors;

labeling said removed successor pin'"'"'s cell as a timing cell;

if said removed successor pin is a clock pin, skipping said removed successor pin; and

if said removed successor pin is not a clock pin, then checking if said removed successor pin is a cell input.

9. The method according to claim 8 wherein if said removed successor pin is a cell input, said processing forward said removed pin further comprises:

checking to see if said removed successor pin has more than one predecessor cell;

if said removed successor pin has more than one predecessor cell, then labeling said more than one predecessor cell as multi-driver load cells, and recursively performing said processing forward said removed pin.

10. The method according to claim 9, wherein:

if said removed successor pin is not a cell input;

or

if said removed successor pin does not have more than one predecessor cell, then recursively performing said processing forward said removed pin.

11. The meted according to claim 4 wherein processing outputs comprises:

building a list of primary outputs.

12. The method according to claim 11 wherein until said list is empty, for each pin encountered, said processing outputs further comprises:

removing said encountered pin from said list;

processing backward said removed pin.

13. The method according to claim 12 wherein processing backward said removed pin comprises:

building a list of predecessors.

14. The method according to claim 13 wherein until said list of predecessors is empty, for each pin encountered, said processing backward said removed pin further comprises:

removing an encountered predecessor pin from said list of predecessors;

labeling said removed predecessor pin'"'"'s cell as a timing cell;

if said removed predecessor pin is a clock pin, skipping said removed predecessor pin; and

if said removed predecessor pin is not a clock pin, then checking if said removed predecessor pin is a cell output.

15. The method according to claim 14 wherein if said removed predecessor pin is a cell output, said processing backward said removed pin further comprises:

labeling successor cells as sink load cells; and

recursively performing said processing backward said removed pin.

16. The method according to claim 14 wherein:

if said removed successor pin is not a cell output then recursively performing said processing backward said removed pin.

17. The method according to claim 4 wherein processing clock inputs comprises:

building a list of primary clock inputs.

18. The method according to claim 17 wherein until said list is empty, for each pin encountered, said processing clock inputs further comprises:

removing said encountered pin from said list;

processing forward said removed pin.

19. The method according to claim 18 wherein processing forward said removed pin comprises:

building a list of successors.

20. The method according to claim 19 wherein until said list of successors is empty, for each pin encountered, said processing forward said removed pin further comprises:

removing an encountered successor pin from said list of successors;

if said removed successor pin is a clock pin, recursively processing forward said removed successor pin; and

if said removed successor pin is not a clock pin, then skipping said removed successor pin.

21. The method according to claim 20 wherein after recursively processing forward said removed successor pin, said processing said clock outputs further comprises:

checking if any successor cells are labeled as timing cells.

22. The method according to claim 21 wherein if any successor cells are labeled as dining cells, said processing said clock outputs further comprises:

labeling said removed successor pin'"'"'s cells as timing cells; and

labeling said successor cells as clock load cells.

23. The method according to claim 21 wherein if no successor cells are labeled as timing cells, ten skipping said removed successor pin.

24. The method according to claim 1 wherein said physical interconnect information models physical and electrical effects of a circuit layout and fabrication process.

25. The method according to claim 24 wherein said physical and elecrical effects include at least one of placement and routing constraints, antenna effects, static timing analysis with RC delay modeling, static timing analysis wit capacitive coupling and noise injection, static timing analysis with IR-drop modeling, and electromigration analysis.

26. The method according to claim 25 wherein placement and routing effects of said at least one block are modeled using one or more of physical dimensions of said at least one block'"'"'s boundaries, physical locations where permitted connections are made to said at least one block'"'"'s pins, and layers used to make said permitted connections.

27. The method according to claim 25 wherein antenna effects are modeled by including in said abstraction all of pin-wires that are electrically connected to each pin, and all diodes, transistor gates, and transistor sources/drains that are connected to pins through those pin-wires.

28. The method according to claim 25 wherein resistance-capacitance (RC) interconnect delay during static timing analysis is modeled by including in said abstraction pin-wires attached to the block'"'"'s primary input/output pins, and wires implementing all pin-nets attached to the cells in a timing shell.

29. The method according to claim 28 wherein sidewall coupling during static timing analysis is modeled by including in said abstraction coupling-wires that may be capacitively coupled to the pin-wires.

30. The method according to claim 29 wherein electromigration effects are modeled, for signal nets using the same information required for static timing analysis.

31. The method according to claim 28 wherein noise injection and delay changes during static timing analysis due to capacitive coupling are modeled by including in said abstraction at least one of:

a) all of the wires on coupling-nets that may be capacitively coupled to pin-wires,

b) coupling-cells that drive these coupling-nets and coupling-cells that are driven by these coupling-nets, with input pins of driving cells being modeled with arrival times and slew values derived during simulation of the block, and

c) transitive-wires that may be coupled to said included coupling-nets.

32. The method according to claim 28 wherein noise injection and delay changes during static timing analysis due to capacitive coupling are modeled by including in said abstraction at least one of:

a) all of the wires on coupling-nets that may be capacitively coupled to the pin-wires

b) coupling-cells that drive these coupling-nets and coupling-cells that are driven by these coupling-nets, with input pins of driving cells being modeled by including an entire cone of combinational logic, up to and including a first latch or flip-flop, that drives these coupling-nets, as well as all of the wires on the coupling-nets that are attached to the pins on additional cells, and

c) transitive-wires that may be coupled to said included coupling-nets.

33. The method according to claim 25 wherein IR drop effects are modeled using a simplified electrical model of a block wherein each pin is modeled as an ideal current sink/source and an associated impedance matrix to model its internal RC-network.

34. The method according to claim 33 wherein electromigration effects are modeled, for power nets, using the same information required for power drop effects.

35. An article comprising a computer-readable medium having instructions stored thereon implementing a method used in producing a design of an integrated circuit design, said circuit design having cells and interconnects, said circuit having a representation that is hierarchically decomposed into a top-level and a plurality of blocks, at least some of the plurality of said blocks being capable of being further hierarchically decomposed and of having a parent block associated therewith, said instructions which when executed causes:

processing at least one of said blocks such tat an abstraction is created that includes physical interconnect information relating to interconnects between components within said at least one block, said physical interconnect information modeling parasitic electrical and physical effects of interconnects upon an estimated behavior of said integrated circuit, wherein said processing includes;

retaining only a sub-set of all of said physical interconnect information which influences physical and electrical behavior of said parent block; and

retaining only a sub-set of cells which influences a logical behavior of said parent block; and

utilizing said abstraction in another development phase performed on said parent block.

36. The article according to claim 35 wherein utilizing includes:

replacing a description of said at least one block with a description of said abstraction.

37. The article according to claim 35, wherein retaining the sub-set of said physical interconnect information and of said cells includes:

determining contents of said at least one block'"'"'s netlist.

38. The article according to claim 37, wherein said contents of the logical shell are determined by:

processing data inputs;

processing outputs; and

processing clock inputs.

39. The article according to claim 38 wherein processing data inputs comprises:

building a list of primary inputs.

40. The article according to claim 39 wherein until said list is empty, for each pin encountered, said processing data inputs further comprises:

removing an encountered pin from said list;

if said removed pin is a clock pin, then skipping said removed pin and continuing to the next pin; and

if said removed pin is not a clock pin, then processing forward said removed pin.

41. The article according to claim 40 wherein processing forward said removed pin comprises:

building a list of successors.

42. The article according to claim 41 wherein until said list of successors is empty, for each pin encountered, said processing forward said removed pin further comprise:

removing an encountered successor pin from said list of successors;

labeling said removed successor pin'"'"'s cell as a timing cell;

if said removed successor pin is a clock pin, skipping said removed successor pin; and

if said removed successor pin is not a clock pin, then checking if said removed successor pin is a cell input.

43. The article according to claim 42 wherein if said removed successor pin is a cell input, said processing forward said removed pin further comprises:

checking to see if said removed successor pin has more than one predecessor cell;

if said removed successor pin has more than one predecessor cell, then labeling said more than one predecessor cell as multi-driver load cells, and recursively performing said processing forward said removed pin.

44. The article according to claim 43 wherein:

if said removed successor pin is not a cell input;

or

if said removed successor pin does not have more than one predecessor cell, then recursively performing said processing forward said removed pin.

45. The article according to claim 38 wherein processing outputs comprises:

building a list of primary outputs.

46. The article according to claim 45 wherein until said list is empty, for each pin encountered, said processing outputs further comprises:

removing said encountered pin from said list;

processing backward said removed pin.

47. The article according to claim 46 wherein processing backward said removed pin comprises:

building a list of predecessors.

48. The article according to claim 47 wherein until said list of predecessors is empty, for each pin encountered, said processing backward said removed pin further comprises:

removing an encountered predecessor pin from said list of predecessors;

labeling said removed predecessor pin'"'"'s cell as a timing cell;

if said removed predecessor pin is a clock pin, skipping said removed predecessor pin; and

if said removed predecessor pin is not a clock pin, then checking if said removed predecessor pin is a cell output.

49. The article according to claim 48 wherein if said removed predecessor pin is a cell output, said processing backward said removed pin further comprises:

labeling successor cells as sink load cells; and

recursively performing said processing backward said removed pin.

50. The article according to claim 48 wherein:

if said removed successor pin is not a cell output then recursively performing said processing backward said removed pin.

51. The article according to claim 38 wherein processing clock inputs comprises:

building a list of primary clock inputs.

52. The article according to claim 51 wherein until said list is empty, for each pin encountered, said processing clock inputs further comprises:

removing said encountered pin from said list;

processing forward said removed pin.

53. The article according to claim 52 wherein processing forward said removed pin comprises:

building a list of successors.

54. The article according to claim 53 wherein until said list of successors is empty, for each pin encountered, said processing forward said removed pin further comprises:

removing an encountered successor pin from said list of successors;

if said removed successor pin is a clock pin, recursively processing forward said removed successor pin; and

if said removed successor pin is not a clock pin, ten skipping said removed successor pin.

55. The article according to claim 54 wherein after recursively processing forward said removed successor pin, said processing said clock outputs further comprises:

checking if any successor cells are labeled as timing cells.

56. The article according to claim 55 wherein if any successor cells are labeled as timing cells, said processing said clock outputs further comprises:

labeling said removed successor pin'"'"'s cells as timing cells; and

labeling said successor cells as clock load cells.

57. The article according to claim 55 wherein if no successor cells are labeled as timing cells, then skipping said removed successor pin.

58. The article according to claim 35 wherein said physical interconnect information includes physical effects of a circuit layout and fabrication process.

59. The article according to claim 58 wherein said physical effects include at least one of placement and routing constraints, antenna effects, static timing analysis with RC delay modeling, static timing analysis with capacitive coupling and noise injection, static timing analysis with IR-drop modeling, and electromigration analysis.

60. The article according to claim 59 wherein placement and routing effects of said at least block are modeled using one or more of physical dimensions of said at least one block'"'"'s boundaries, physical locations where permitted connections are made to said block'"'"'s pins, and layers used to make said permitted connections.

61. The article according to claim 59 wherein antenna effects are modeled by including in said abstraction all of pin-wires that are electrically connected to each pin, and all diodes, transistor gates, and transistor sources/drains that are connected to pins through those pin-wires.

62. The article according to claim 59 wherein resistance-capacitance (RC) interconnect delay during static timing analysis is modeled by including in said abstraction pin-wires attached to the block'"'"'s primary input/output pins, and wires implementing all pin-nets attached to the cells in a timing shell.

63. The article according to claim 62 wherein sidewall coupling analysis during static timing analysis is modeled by including in said abstraction coupling-wires that may be capacitively coupled to the pin-wires.

64. The article according to claim 63 wherein electromigration effects are modeled, for signal nets using the same information required for static timing analysis.

65. The article according to claim 62 wherein noise injection and delay changes during static timing analysis due to capacitive coupling are modeled by including in said abstraction at least one of:

a) all of wires on the coupling-nets that may be capacitively coupled to the pin-wires,

b) coupling-cells that drive these coupling-nets and coupling-cells that are driven by these coupling-nets, with input pins of driving cells being modeled with arrival times and slew values derived during simulation of the block, and

c) transitive-wires that may be coupled to said included coupling-nets.

66. The article according to claim 62 wherein noise injection and delay changes during static timing analysis due to capacitive coupling are modeled by including in said abstraction at least one of:

a) all of the wires on coupling-nets that may be capacitively coupled to the pin-wires,

b) coupling-cells that drive these coupling-nets and coupling-cells that are driven by these coupling-nets, with input pins of driving cells being modeled by including an entire cone of combinational logic, up to and including a first latch or flip-flop, that drives these coupling-nets, as well as all of the wires on the coupling-nets that are attached to the pins on additional cells, and

c) the transitive-wires that may be coupled to said included coupling-nets.

67. The article according to claim 59 wherein IR drop effects are modeled using a simplified electrical model of a block wherein each pin is modeled as an ideal current sink/source and an associated impedance matrix to model its internal RC-network.

68. The article according to claim 67 wherein electromigration effects are modeled, for power nets, using the same information required for power drop effects.