Semiconductor device, and design method, inspection method, and design program therefor

• US 7,103,864 B2
• Filed: 10/08/2003
• Issued: 09/05/2006
• Est. Priority Date: 11/01/2002
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: Umc Japan
• Inventors: Isobe, Shinobu
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US10/681,993
• Publication Number:
  US 20050055651A1
• Time in Patent Office: 1,063 Days
• Field of Search: 716/9, 716/10, 716/13, 716/14
• US Class Current: 716/122
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/318364 as a result of hardware simulation, e.g. in an HDL environment computer-aided simulation of circuits G06F30/3308

Abstract

A design method for automatically determining layout of a multilayer semiconductor device which has circuit blocks formed on a semiconductor substrate and measurement terminals for measuring voltage, logic state, or the like, on wiring lines for connecting the circuit blocks. The method includes the steps of registering measurement terminals as cells in design rules, together with the circuit blocks wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and the measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, which is formed in any layer of the semiconductor device; planar-arranging the measurement terminals and the circuit blocks; and establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

Claims

1. A design method of designing a multilayer semiconductor device which includes a plurality of circuit blocks formed on a semiconductor substrate, the method comprising the steps of:

registering measurement terminals as cells in design rules, together with the circuit blocks, wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and each measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, and said wiring line is formed in any layer of the semiconductor device;

planar-arranging the measurement terminals and the circuit blocks based on the design rules; and

establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.

2. A design method as claimed in claim 1, wherein in the step of establishing the connection of each wiring line, the connection is performed based on a net list which stores data of each measurement terminal and terminations of a wiring line on which each measurement terminal is provided.

3. A design program embedded on a computer-readable medium for making a computer execute an operation of designing a multilayer semiconductor device which includes a plurality of circuit blocks formed on a semiconductor substrate, the operation comprising the steps of:

registering measurement terminals as cells in design rules, together with the circuit blocks, wherein each measurement terminal has an electrode formed in an uppermost layer of the semiconductor device, and each measurement terminal is connectable to a wiring line for connecting any two of the circuit blocks, and said wiring line is formed in any layer of the semiconductor device;

planar-arranging the measurement terminals and the circuit blocks based on the design rules; and

establishing connection of each wiring line, which extends from one of the circuit blocks, via one of the measurement terminals.