Method for manufacturing a power bus on a chip

• US 7,103,867 B2
• Filed: 10/27/2004
• Issued: 09/05/2006
• Est. Priority Date: 02/10/1992
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Lin, Chong Ming, Hoang, Hy, Chuang, Tatao, Long, Tran
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US10/973,896
• Publication Number:
  US 20050086625A1
• Time in Patent Office: 678 Days
• Field of Search: 716/1, 716/2, 716/9, 716/12, 716/15, 716/17
• US Class Current: 716/54
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for manufacturing a power bus on a chip, where the power bus has slits generated therein. The present invention relates to a method to manufacture a power bus in which the reference to a layout data base shows the coordinate location of the power buses in the chip. A height and width for the power bus is calculated based on its coordinates. Based on the height and width of the power buses and the predetermined size and spacing between power slits, a number of power slits to be generated is determined. These power slits are then generated by adding the power slits to the power bus in the coordinates of the layout database. The method of the present invention also generates power slits for use in manufacturing power buses on a chip for cases in which the power buses overlap.

Claims

1. A computer program product for defining power slits in a power bus located on a chip, comprising:

a computer usable medium having computer readable program code means embodied in said computer usable medium for causing an application program to execute on an operating system of a computer, said computer readable program code means comprising;

a computer readable first program code means for locating the power bus in a defined region of the chip;

a computer readable second program code means for determining a first number of power slits to be generated in a horizontal direction of the power bus;

a computer readable third program code means for determining a second number of power slits to be generated in a vertical direction of the power bus; and

a computer readable fourth program code means for defining the power slits in the horizontal and vertical directions of the power bus according to said first and second numbers of power slits calculated by the second program code means and the third program code means, respectively.

2. The computer program product of claim 1, further comprising:

a computer readable fifth program code means for determining a width for the power bus; and

a computer readable sixth program code means for determining a length for the power bus;

wherein said second program code means includes means for dividing the width of the power bus by a predetermined maximum width of the power slits plus a predetermined first spacing distance between the power slits to determine the first number of power slits to be generated in a horizontal direction of the power bus; and

wherein said third program code means includes means for dividing the length of the power bus by a predetermined minimum length of the power slits plus a predetermined second spacing distance between the power slits in the lengthwise direction to determine a second number of power slits to be generated in a vertical direction of the power bus.

3. The computer program product of claim 2, wherein said fifth and sixth program code means comprise:

means for assigning a first starting-point and a first endpoint corresponding to boundaries of the power bus in a horizontal direction;

means for subtracting the first starting-point from the first endpoint resulting in a first absolute value;

means for assigning a second starting-point and a second endpoint corresponding to boundaries of the power bus in a vertical direction;

means for subtracting the second starting-point and the second endpoint resulting in a second absolute value;

means for comparing the first absolute value with the second absolute value to determine which is greater;

means for assigning the greater value as the length of the power bus; and

means for assigning the lesser value as the width of the power bus.

4. The computer program product of claim 3, further comprising:

a computer readable seventh program code means for receiving parameters indicating coordinate value locations for the chip;

wherein the first and second starting-points and the first and second endpoints are coordinate locations obtained from the coordinate values received by the seventh program code means.

5. The computer program product of claim 2, further comprising:

a computer readable seventh program code means for comparing the width for the power bus determined by the fifth program code means to a minimum standard value and invoking the first program code means if the minimum standard value is greater than the width for the power bus.

6. A computer program product for defining power slits in a power bus, comprising:

a computer usable medium having computer readable program code means embodied in said computer usable medium for causing an application program to execute on an operating system of a computer, said computer readable program code means comprising;

a computer readable first program code means for locating a power bus in a defined region of a chip;

a computer readable second program code means for determining a first number of power slits to be generated in a horizontal direction of the power bus;

a computer readable third program code means for determining a second number of power slits to be generated in a vertical direction of the power bus;

a computer readable fourth program code means for defining the power slits in the horizontal and vertical directions of the power bus according to said first and second numbers of power slits calculated by the second program code means and the third program code means, respectively; and

a computer readable fifth program code means for invoking the first, second, third and fourth program code means until all power buses in the defined region have power slits.

7. The computer program product of claim 6, further comprising:

a computer readable sixth program code means for determining a width for the power bus; and

a computer readable seventh program code means for determining a length for the power bus;

wherein the second program code means includes means for dividing the width of the power bus by a predetermined maximum width of the power slits plus a predetermined first spacing distance between the power slits to determine the first number of power slits to be generated in a horizontal direction of the power bus; and

wherein said third program code means includes means for dividing the length of the power bus by a predetermined minimum length of the power slits plus a predetermined second spacing distance between the power slits in the lengthwise direction to determine a second number of power slits to be generated in a vertical direction of the power bus.

8. The computer program product of claim 6, further comprising:

a computer readable sixth program code means for identifying if any power buses in the defined region overlap to form an orthogonal cross section;

a computer readable seventh program code means for removing all power slits in the orthogonal cross section;

a computer readable eighth program code means for extending first pointer line(s) from a first power slit(s) of a first power bus to an opposite boundary side of the cross section to connect the first power slits(s) of the first power bus;

a computer readable ninth program code means for extending second pointer line(s) from a second power slit(s) of a second power bus to an opposite boundary side of the cross section from the second power slits of the second power bus;

a computer readable tenth program code means for intersecting, logically, the first pointer line(s) with said second pointer line(s) forming a defined hole indicating where to generate power slits.

9. The computer program product of claim 8, wherein said tenth program code means comprises means for logically ANDing the first pointer line(s) with the second pointer line(s) to form defined holes indicating where to generate power slits.

10. The computer program product of claim 9, wherein said sixth program code means comprises means for evaluating logically where two buses share coordinate values that intersect.

11. The computer program product of claim 10, wherein said means for evaluating includes means for searching for two buses that have overlapping coordinate values.

12. The computer program product of claim 8, wherein said eighth program code means includes means for extending pointer lines in a 90°

direction.

13. The computer program product of claim 8, wherein said eighth program code means includes means for extending pointer lines in a 180°

direction.

14. The computer program product of claim 8, wherein said ninth program code means includes means for extending pointer lines in a 90°

direction.

15. The computer program product of claim 8, wherein said ninth program code means includes means for extending pointer lines in a 180°

direction.

16. A computer program product for defining slits in a power bus located on a chip, comprising:

a computer usable medium having computer readable program code means embodied in said computer usable medium for causing an application program to execute on an operating system of a computer, said computer readable program code means comprising;

a computer readable first program code means for determining a number of power slits to be generated in the power bus; and

a computer readable second program code means for defining the power slits in the power bus according to the number of power slits calculated by the first program code means.