Nonplanar transistors with metal gate electrodes

• US 7,105,390 B2
• Filed: 12/30/2003
• Issued: 09/12/2006
• Est. Priority Date: 12/30/2003
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Doczy, Mark L., Doyle, Brian S., Brask, Justin K.
• Primary Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US10/750,061
• Publication Number:
  US 20050148137A1
• Time in Patent Office: 987 Days
• Field of Search: 438/149, 438/199, 438/197, 438/157, 438/283, 438/303, 438/231, 438/275
• US Class Current: 438/149
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are uniformed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate wherein said semiconductor body has a channel region with a p type conductivity;

forming a gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode on said gate dielectric and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body, wherein said gate electrode comprises a metal film formed directly adjacent to said gate dielectric wherein said gate electrode has a work function between 3.9–

4.2 eV; and

forming a pair of source/drain regions formed in said semiconductor body on opposite sides of said gate electrode.

2. The method of claim 1 wherein said gate electrode comprises only said metal film.

3. The method of claim 1 wherein said gate electrode further comprises a doped silicon film formed on said metal film.

4. The method of claim 3 wherein said metal film is formed to a thickness between 25–

100 Å and

said doped silicon film is formed to a thickness between 500–

3000 Å

.

5. The method of claim 1 wherein said gate dielectric is selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, PZT, BST, aluminum oxide, and silicates thereof.

6. A method of forming a CMOS integrated circuit comprising:

forming a first and a second semiconductor body on an insulating substrate said first and second semiconductor bodies each having a top surface and a bottom surface and a pair of laterally opposite sidewalls;

forming a first silicon sacrificial gate electrode above said top surface of said first semiconductor body and adjacent to said laterally opposite sidewalls of said semiconductor body, and forming a second silicon sacrificial gate electrode above said top surface of said second semiconductor body and adjacent to said laterally opposite sidewalls of said second semiconductor body;

placing n type dopants into said first silicon sacrificial gate electrode and into said semiconductor body on opposite sides of said first silicon sacrificial gate electrode;

placing p type dopants into said second sacrificial silicon gate electrode and into said second semiconductor body on opposite sides of said second sacrificial gate electrode;

activating said n type and p type dopants so that said n type and p type dopants become substitutional with silicon atoms in said first and second sacrificial silicon gate electrodes;

forming a dielectric layer over said first and second sacrificial gate electrode and over said first and second semiconductor bodies and over said insulating substrate;

planarizing said dielectric layer until the top surface of said dielectric layer is planar with the top surface of said first and second silicon sacrificial gate electrodes and said first and second sacrificial gate electrodes exposed;

removing said first sacrificial gate electrode without removing said second sacrificial gate electrode to form a first opening which exposes the channel region of said first semiconductor body;

forming a gate dielectric layer in said first opening on said top surface and said sidewalls of the channel region of said first semiconductor body;

blanket depositing a first gate electrode material on said gate dielectric layer in said opening on said top surface of said semiconductor body and adjacent to said gate dielectric on said sidewalls of said semiconductor body, wherein said first gate electrode material comprises a first metal film formed directly on and adjacent to said first gate dielectric layer;

removing said first gate electrode material from the top surface of said dielectric film to form a first gate electrode;

removing said second sacrificial gate electrode to form a second opening which exposes the second channel region of said second semiconductor body;

forming a second gate dielectric layer in said second opening on said top surface and sidewalls of said channel region of said second semiconductor body;

blanket depositing a second gate electrode material on said second gate dielectric layer in said second opening on said top surface of said second semiconductor body and adjacent to said second gate dielectric layer on said sidewalls of said semiconductor body, wherein said second gate electrode material comprises a second metal film formed directly on said gate dielectric layer wherein said second metal film is different than said first metal film; and

removing said second gate electrode material from the top surface of said dielectric film to form a second gate electrode.

7. The method of claim 6 wherein said first and second semiconductor bodies are formed from single crystalline silicon.

8. The method claim 6 wherein said insulating substrate comprises a lower monocrystalline silicon substrate and a top silicon oxide insulating film.

9. The method of claim 6 wherein said first metal film is selected from the group consisting of hafnium, zirconium, titanium, tantalum, aluminum, with a workfunction between about 3.9 eV and about 4.2 eV.

10. The method of claim 6 wherein said second metal film is selected from the group consisting of ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, with a workfunction between about 4.9 eV and 5.2 eV.

11. The method of claim 6 wherein said first sacrificial gate electrode is removed without masking said second sacrificial gate electrode.

12. The method of claim 6 wherein said first gate electrode is removed utilizing an etchant selected from the group consisting of ammonium hydroxide and potassium hydroxide.

13. The method of claim 6 wherein said second sacrificial gate electrode is removed utilizing a wet etchant comprising tetra methyl ammonia hydroxide.

14. The method of claim 6 further comprising forming a first pair of sidewall spacers adjacent to said laterally opposite sidewalls of said first sacrificial gate electrode and forming a second pair of sidewall spacers adjacent to laterally opposite sidewalls of said second sacrificial gate electrode.

15. The method of claim 6 further comprising forming silicon on said first and second semiconductor bodies adjacent to said sidewall spacers.

16. The method of claim 15 further comprising forming silicide on said silicon formed on said first semiconductor body adjacent to said first sidewall spacers and forming silicide on said silicon film formed on said second semiconductor body adjacent to said second sidewall spacers.

17. A method of forming an integrated circuit comprising:

forming a first sacrificial gate electrode over a channel region of a first semiconductor body and forming a second sacrificial gate electrode over a second channel region of a second semiconductor body;

altering said first sacrificial gate electrode and/or said second sacrificial gate electrode such that said first sacrificial gate electrode can be etched with an etchant without etching said second sacrificial gate electrode;

forming a dielectric layer over said first sacrificial gate electrode, and said second sacrificial gate electrode, and said first semiconductor body and said second semiconductor body;

planarizing said dielectric layer so as to expose said top surface of said first sacrificial gate electrode and said second sacrificial gate electrode;

after altering said first sacrificial gate electrode and/or said second sacrificial gate electrode etching said first sacrificial gate electrode with said etchant without etching said second sacrificial gate electrode to form an opening and expose said channel region of said first semiconductor body;

depositing a first metal film in said opening and over the top of said semiconductor body and adjacent to the sidewalls of said semiconductor body and on the top surface of said dielectric layer;

removing said first metal film from the top of said dielectric layer to form a metal gate electrode;

removing said second sacrificial gate electrode material to form a second opening;

forming a second metal film different than said first metal film over said dielectric layer and into said second opening; and

removing said second metal film from the top surface of said dielectric layer to form a second metal gate electrode.

18. The semiconductor device of claim 17 wherein first metal film has a work function between 3.9 eV and 4.2 eV.

19. The method of claim 17 wherein said second metal film has a work function between 4.9 eV to 5.2 eV.

20. The method of claim 17 wherein said first sacrificial gate electrode and/or said second sacrificial gate electrode are altered by placing dopants therein.

21. The method of claim 17 wherein both said first and said second sacrificial gate electrode materials are exposed to said etchant.

22. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate wherein said semiconductor body has a channel region with a n type conductivity;

forming a gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body;

forming a gate electrode on said gate dielectric and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body, wherein said gate electrode comprises a metal film formed directly adjacent to said gate dielectric wherein said gate electrode has a work function between 4.9–

5.2 eV; and

forming a pair of source/drain regions formed in said semiconductor body on opposite sides of said gate electrode.

23. The method of claim 22 wherein said gate electrode comprises only said metal film.

24. The method of claim 22 wherein said gate electrode further comprises a doped silicon film formed on said metal film.

25. The method of claim 24 wherein said metal film is formed to a thickness between 25–

100 Å and

said doped silicon film is formed to a thickness between 500–

3000 Å

.

26. The method of claim 22 wherein said gate dielectric is selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, PZT, BST, aluminum oxide, and silicates thereof.

27. A method of forming a CMOS integrated circuit comprising:

forming a first semiconductor body having a top surface and laterally opposite sidewalls on a substrate, wherein said first semiconductor body has a channel region with an p type conductivity and forming a second semiconductor body having a top surface and laterally opposite sidewalls on said substrate, wherein said second semiconductor body has a channel region with an n type conductivity;

forming a first gate dielectric layer on said channel region of said first semiconductor body and forming a second gate dielectric layer on said channel region of said second semiconductor body;

forming a first gate electrode on said first gate dielectric layer wherein said first gate electrode includes a first metal film formed directly on said first gate dielectric layer and wherein said first gate electrode has a work function between 3.9–

4.2 eV and forming a second gate electrode on said second gate dielectric layer wherein said second gate electrode has a second metal film formed directly on said second gate dielectric layer and wherein said second gate electrode has a work function between 4.9–

5.2 eV; and

forming a first pair of source/drain region in said first semiconductor body on opposite sides of said first gate electrode and forming a second pair of source/drain regions in said second semiconductor body on opposite sides of said second gate electrode.

28. The method of claim 27 wherein said first gate electrode comprises only said first metal film and said second gate electrode comprises only said second metal film.

29. The method of claim 27 wherein said first gate electrode and said second gate electrode further comprise a doped silicon film formed on said first metal film and said second metal film.

30. The method of claim 29 wherein said first metal film and said second metal film are formed to a thickness between 25–

100 Å and

said doped silicon film is formed to a thickness between 500–

300 Å

.

31. The method of claim 27 wherein said first gate dielectric layer and second gate dielectric layer are selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, PZT, BST, aluminum oxide and silicates thereof.

32. A method of forming a CMOS integrated circuit comprising:

a first semiconductor body having a top surface and laterally opposite sidewalls of a substrate wherein said first semiconductor body has a channel region with a p type conductivity, and forming a second semiconductor body having a top surface and laterally opposite sidewalls on said substrate, wherein said second semiconductor body has a channel region with an n type conductivity;

forming a first gate dielectric layer on said channel region of said first semiconductor body and forming a second gate dielectric layer on said channel region of said second semiconductor body;

forming a first gate electrode on said first dielectric layer wherein said first gate electrode includes a first metal film formed directly on said first gate dielectric layer, and forming a second gate electrode on said second gate dielectric layer, wherein said second gate electrode has a second metal film formed directly on said second gate dielectric layer, wherein said second gate electrode has a work function of approximately 1.0 eV or greater than the work function of said first gate electrode.

33. The method of claim 32 wherein said first gate electrode comprises only said first metal film and said second gate electrode comprises only said second metal film.

34. The method of claim 33 wherein said first gate electrode and said second gate electrode further comprise a doped silicon film formed on said first metal film and said second metal film.

35. The method of claim 34 wherein said first metal film and said second metal film are formed to a thickness between 25–

100 Å and

said doped silicon film is formed to a thickness between 500–

300 Å

.

36. The method of claim 32 wherein said first gate dielectric layer and second gate dielectric layer are selected from the group consisting of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, PZT, BST, aluminum oxide and silicates thereof.