Planar pedestal multi gate device
First Claim
Patent Images
1. Method of forming a transistor comprising:
- disposing a planar platform of silicon atop a support structure of oxide which is atop a substrate;
wherein the support structure is disposed beneath the planar platform;
forming multiple gate structures both atop and beneath the planar platform; and
forming source and drain diffusions within the planar platform.
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Abstract
A method of forming a transistor comprises disposing a planar platform (or pedestal, or layer) of silicon atop a support structure of oxide which is atop a substrate; forming gate structures both atop and beneath the planar platform; and forming source and drain diffusions within the planar platform. The gate structures which are formed beneath the planar platform may smaller than the planar platform, and may be aligned with the gate structures which are formed atop the planar platform. A transistor formed by the method is also disclosed.
22 Citations
17 Claims
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1. Method of forming a transistor comprising:
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disposing a planar platform of silicon atop a support structure of oxide which is atop a substrate; wherein the support structure is disposed beneath the planar platform; forming multiple gate structures both atop and beneath the planar platform; and forming source and drain diffusions within the planar platform. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. Method of forming a transistor comprising:
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providing an SOI wafer comprising a handle substrate, a buried oxide layer (BOX) disposed atop the handle substrate and a silicon-on-insulator (SOI) layer disposed atop the buried oxide layer; in a first etching step, patterning the SOI layer to become the active silicon layer of an SOI transistor, wherein a portion of the buried oxide layer is underneath the patterned SOI layer and other portions of the buried oxide layer are not underneath the patterned SOI layer, and wherein a top surface of the patterned SOI layer is exposed; in a second etching step, etching the portions of the buried oxide layer which are not underneath the patterned SOI layer, thereby exposing a portion of a top surface of the handle substrate; in a third etching step, removing the buried oxide layer from under the patterned SOI layer to form a standoff structure, thereby exposing a portion of a bottom surface of the patterned SOI layer, performing gate oxidation, thereby forming gate oxide on the exposed surfaces of the patterned SOI layer; depositing gate electrode material atop the handle substrate and covering the standoff structure as well as the patterned SOI layer; and in a fourth etching step, etching the gate electrode material to form at least one gate stack atop the patterned SOI layer. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification