Heterojunction tunneling diodes and process for fabricating same

• US 7,105,866 B2
• Filed: 08/05/2004
• Issued: 09/12/2006
• Est. Priority Date: 07/24/2000
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Ramdani, Jamal, Droopad, Ravindranath, El-Zein, Nada, Eisenbeiser, Kurt
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US10/911,624
• Publication Number:
  US 20050056210A1
• Time in Patent Office: 768 Days
• Field of Search: 257/44, 257/46, 257/51, 257/52, 257/75, 257/74, 257/104, 257/106, 257/67
• US Class Current: 257/104
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/882 Resonant tunneling diodes, i.e. RTD, RTBD

Abstract

High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Claims

1. A monolithic integrated circuit comprising:

an MOS circuit formed at least partially in a monocrystalline substrate;

a monocrystalline compound semiconductor layer overlying the monocrystalline substrate; and

a tunnel diode formed at least partially in the monocrystalline compound semiconductor layer, the tunnel diode electrically coupled to the MOS circuit.

2. The monolithic integrated circuit of claim 1 wherein the MOS circuit comprises an MOS transistor having a drain region and the tunnel diode is electrically coupled to the drain region.

3. The monolithic integrated circuit of claim 2 further comprising a second tunnel diode coupled to the drain region in series with the tunnel diode.

4. The monolithic integrated circuit of claim 1 wherein the MOS circuit comprises an MOS transistor having a drain region and the tunnel diode is formed overlying and electrically coupled to the drain region.

5. The monolithic integrated circuit of claim 1 wherein the MOS circuit comprises an MOS transistor having a gate electrode and the tunnel diode is formed overlying and electrically coupled to the gate electrode.

6. The monolithic integrated circuit of claim 1 wherein the MOS circuit comprises a digital circuit.

7. The monolithic integrated circuit of claim 1 wherein the tunnel diode comprises an interband tunnel diode.

8. The monolithic integrated circuit of claim 1 wherein the tunnel diode comprises an intraband tunnel diode.