Semiconductor device

• US 7,105,871 B2
• Filed: 12/09/2003
• Issued: 09/12/2006
• Est. Priority Date: 12/18/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: eASIC Corporation (Intel Corporation)
• Inventors: Apostol, Adrian, Iacobut, Romeo, Or-Bach, Zvi, Cooke, Laurence
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/730,064
• Publication Number:
  US 20040161878A1
• Time in Patent Office: 1,008 Days
• Field of Search: 257/202, 257/203, 257/620, 257/734, 257/773, 257/786
• US Class Current: 257/203
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor device may include a borderless logic array and area I/Os. The logic array may comprise a repeating core, and at least one of the area I/Os may be a configurable I/O. Furthermore, the configurable I/O may comprise at least one metal layer that is the same for all I/O configurations.

Claims

1. A semiconductor device comprising:

a borderless logic array comprising repeating cores;

area I/Os, wherein at least one of said area I/Os is located in said semiconductor device such that some of said repeating cores are placed adjacent to two opposite sides of the area I/O;

wherein at least one of said area I/Os is a configurable I/O, and wherein said configurable I/O comprises at least one metal layer that is the same for all I/O configurations.

2. A semiconductor device according to claim 1, wherein said configurable I/O comprises:

at least two electronic components; and

multiple possible connections among said electronic components, wherein at least one custom via layer is used to complete at least one of said possible connections to configure said configurable I/O.

3. A semiconductor device according to claim 1, wherein some of said area I/Os are arranged in spaced parallel lines.

4. A semiconductor wafer comprising:

a borderless logic array, wherein said borderless logic array comprises a repeating module containing logic cells and I/O cells and a redistribution layer for redistributing at least some of said I/O cells'"'"' connections to pads used in packaging, wherein at least one of said I/O cells comprises an area I/O having logic cells adjacent to opposite sides of the area I/O.

5. A semiconductor device according to claim 4, wherein some of said area I/Os are arranged in spaced parallel lines.

6. A semiconductor wafer according to claim 5, wherein spaced parallel lines are spaced at least 0.2 mm apart but less than 3 mm apart.

7. A semiconductor wafer according to claim 4, wherein said repeating module comprises at least two metal layers.

8. A semiconductor wafer according to claim 7, wherein at least one of said metal layers comprises a repeating pattern.

9. A semiconductor wafer according to claim 7, wherein each of said metal layers comprises a repeating pattern.

10. A semiconductor wafer according to claim 7, wherein additional custom layers are arranged to define a specific die size on said semiconductor wafer.

11. A semiconductor wafer according to claim 7, wherein additional custom layers are arranged to define at least two different die sizes on said semiconductor wafer.

12. A semiconductor wafer according to claim 4, wherein at least one of said I/O cells comprises:

at least two electronic components; and

multiple possible connections among said electronic components, wherein at least one custom via layer is used to complete at least one of said possible connections to configure at least one of said I/O cells.

13. A semiconductor device comprising:

a borderless logic array comprising repeating cores;

area I/Os, wherein at least one of said area I/Os is located in said semiconductor device such that some of said repeating cores are placed adjacent to two opposite sides of the area I/O; and

wherein said logic array comprises a repeating core and a redistribution layer for redistributing at least some of said area I/O connections to pads used in packaging.

14. A semiconductor device comprising:

a borderless logic array;

area I/Os, wherein at least one of said area I/Os is located in said semiconductor device such that there is logic adjacent to two opposite sides of the area I/O; and

wherein at least one of said area I/Os is a configurable I/O, and a redistribution layer for redistributing at least some of said area I/O connections to pads used in packaging.

15. A logic array device comprising:

a borderless logic array;

area I/Os, wherein at least one of said area I/Os is located in said semiconductor device such that there is logic adjacent to two opposite sides of the area I/O; and

wherein at least one of said area I/Os is a configurable I/O, and wherein said configurable I/O comprises at least one metal layer that is the same for all I/O configurations.

16. A logic array device according to claim 15, wherein said configurable I/O further comprises:

at least two electronic components; and

multiple possible connections among said electronic components, wherein a custom via layer is used to complete at least one of said possible connections to configure said configurable I/O.

17. A semiconductor device comprising:

a continuous logic array comprising repeating cores;

area I/Os, wherein at least one of said area I/Os is located in said semiconductor device such that some of said repeating cores are placed adjacent to two opposite sides of the area I/O;

wherein at least one of said area I/Os is a configurable I/O, and wherein said configurable I/O comprises at least two metal layers that are the same for all I/O configurations.

18. A semiconductor device comprising:

area I/Os, where at least one of said area I/Os is located in said semiconductor device such that logic is placed adjacent to two opposite sides of the area I/O;

wherein at least one of said area I/Os is a configurable I/O, and wherein said configurable I/O comprises at least two metal layers that are the same for all I/O configurations.

19. A semiconductor wafer comprising:

a continuous logic array, wherein said continuous logic array comprises a repeating module containing logic cells and I/O cells and a redistribution layer for redistributing at least some of said I/O cells'"'"' connections to pads used in packaging;

wherein at least one of said I/O cells comprises area I/O having logic cells adjacent to opposite sides of the area I/O.

20. A semiconductor wafer comprising:

a logic array, said logic array comprising a repeating module containing logic cells and I/O cells and a redistribution layer for redistributing at least some of said I/O cells'"'"' connections to pads used in packaging;

wherein at least one of said I/O cells comprises an area I/O having logic cells adjacent to opposite sides of the area I/O.

21. A semiconductor wafer according to claim 20, wherein said I/O cells are arranged in spaced parallel lines.

22. A semiconductor wafer according to claim 21, wherein said spaced parallel lines are spaced at least 0.2 mm apart but less than 3 mm apart.

23. A semiconductor device according to claim 20, wherein said repeating module comprises at least two metal layers, wherein at least one of said two metal layers comprises a repeating pattern.