Structure of dummy pattern in semiconductor device

• US 7,105,927 B2
• Filed: 05/19/2005
• Issued: 09/12/2006
• Est. Priority Date: 05/28/2004
• Status: Active Grant

• Current Assignee: SK Keyfoundry Incorporated
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Lee, Se Young
• Primary Examiner(s): Soward, Ida M.
• Application Number:
  US11/132,597
• Publication Number:
  US 20050263904A1
• Time in Patent Office: 481 Days
• Field of Search: 257/48, 257/734, 257/773, 257/401, 257/496, 257/758, 257/798
• US Class Current: 257/773
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed herein is a dummy pattern structure of a semiconductor device. The dummy pattern structure may include daughter dummy patterns respectively formed at places corresponding to vertexes of polygons in regions where metal wirings are not formed in an interlayer insulating film where metal wirings are formed, thus being arranged in the whole region while constituting a polygon shape, and mother dummy patterns respectively formed at places corresponding to the middles of the polygon, which is formed by the daughter dummy patterns. Generation of metal residues in a region where metal wirings are not formed when the metal wirings are formed by means of a damascene process are prevented. Also, a delamination phenomenon that interlayer insulating films are fallen apart can be prevented.

Claims

1. A dummy pattern structure of a semiconductor device, comprising:

first dummy patterns formed between metal wirings in an interlayer insulating film where metal wirings are formed, wherein the first dummy patterns respectively formed at places corresponding to vertexes of polygons thus being arranged with constituting a polygon shape; and

second dummy patterns respectively formed at places corresponding to the middles of the polygon which is formed by the first dummy patterns.

2. The dummy pattern structure as claimed in claim 1, wherein the first dummy patterns and the second dummy patterns are formed by the same process as a process of forming a metal wiring.

3. The dummy pattern structure as claimed in claim 1, wherein the first dummy patterns, the second dummy patterns and the metal wiring are formed by means of a damascene process.

4. The dummy pattern structure as claimed in claim 1, wherein the first dummy patterns are arranged in the form of one of a triangle, a pentagon, a hexagon and an octagon.

5. The dummy pattern structure as claimed in claim 1, wherein the first dummy patterns are arranged in the form of one of a regular triangle, a regular pentagon, a regular hexagon and a regular octagon.

6. The dummy pattern structure as claimed in claim 1, wherein a distance between the first dummy patterns is 3 to 100 μ

m.

7. The dummy pattern structure as claimed in claim 1, wherein a distance between the first dummy pattern and the second dummy pattern is 3 to 100 μ

m.

8. The dummy pattern structure as claimed in claim 1, wherein the second dummy patterns and the first dummy patterns are formed to have the density of 10 to 50% of the entire region where the second dummy patterns and the first dummy patterns are formed.

9. The dummy pattern structure as claimed in claim 1, wherein the second dummy patterns and the first dummy patterns are formed to have the same density as the density of the metal wiring in the region where the metal wiring is formed, or the density 15% higher than the density of the metal wiring in the region where the metal wiring is formed.

10. The dummy pattern structure as claimed in claim 1, wherein each of the first dummy patterns and the second dummy patterns is formed in a variety of polygonal shapes, wherein the first dummy patterns and the second dummy patterns are formed in the same polygon among the variety of the polygonal shapes, or have a shape in which the variety of the polygons are mixed.

11. The dummy pattern structure as claimed in claim 10, wherein in each of the first dummy patterns and the second dummy patterns, the length of one side of the polygon is 3 to 100 μ

m.

12. The dummy pattern structure as claimed in claim 10, wherein an area of each of the first dummy patterns and the second dummy patterns is 9 to 10000 μ

m².

13. The dummy pattern structure as claimed in claim 10, wherein the first dummy patterns and the second dummy patterns have the polygon of the same area, the second dummy patterns have an area wider than that of the first dummy pattern, or the first dummy patterns have an area wider than that of the second dummy pattern.

14. The dummy pattern structure as claimed in claim 1, wherein an area of the region where the second dummy patterns and the first dummy patterns are formed is 250000 μ

m² or less.

15. The dummy pattern structure as claimed in claim 14, wherein if the area of a region where the second dummy patterns and the first dummy patterns are formed is 250000 μ

m² or more, pad patterns of an area wider than that of the dummy patterns are further formed.

16. The dummy pattern structure as claimed in claim 15, wherein the pad patterns are formed to have the density of 10 to 40%.