Reliability comparator with hysteresis

• US 7,106,107 B2
• Filed: 01/31/2005
• Issued: 09/12/2006
• Est. Priority Date: 01/31/2005
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Bhattacharya, Dipankar, Morris, Bernard L., Wilson, William B., Kriz, John Christopher
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US11/047,388
• Publication Number:
  US 20060170462A1
• Time in Patent Office: 589 Days
• Field of Search: 327/77, 327/78, 327/87, 327/205, 327/206
• US Class Current: 327/77
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 3/3565 Bistables with hysteresis, e.g. Schmitt trigger

Abstract

A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal. The comparator circuit further includes a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage. The comparator is operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal. A hysteresis circuit is included in the comparator circuit for selectively controlling a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator. The comparator circuit includes a voltage clamp operative to limit a voltage applied to one or more devices in the control circuit, the comparator, and/or the hysteresis circuit to less than the second voltage.

Claims

1. A comparator circuit, comprising:

a reference generator connecting to a first source providing a first voltage, the reference generator being operative to generate a reference signal and including a control circuit selectively operable in one of at least a first mode and a second mode in response to a first control signal applied to the reference generator, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal;

a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage, the comparator being operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal;

a hysteresis circuit operative to selectively control a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator; and

a voltage clamp operative to limit a voltage applied to at least one of the control circuit, the comparator, and the hysteresis circuit to less than the second voltage.

2. The circuit of claim 1, wherein the reference generator comprises a plurality of resistors connected in series between the first source and a third source providing a third voltage, the third voltage being less than the first voltage, a level of the reference signal being controlled at least in part as a function of values of the resistors.

3. The circuit of claim 1, wherein the reference generator comprises at least first, second and third resistors having first, second and third resistances, respectively, associated therewith, the first resistor connecting at a first end to the first source, a second end of the first resistor being connected to a first end of the second resistor at a first node, a second end of the second resistor being connected to a first end of the third resistor at a second node, and a second end of the third resistor being connected to the control circuit, the reference signal being generated at the first node, a level of the reference signal being controlled at least in part as a function of values of at least one of the first, second and third resistors.

4. The circuit of claim 3, wherein the hysteresis circuit is operative to selectively connect a substantially low-resistance electrical path across at least one of the second and third resistors in response to a second control signal, the second control signal being a function of the output signal of the comparator.

5. The circuit of claim 3, wherein the hysteresis circuit is configured such that when the output signal of the comparator is a first logic level, the reference signal has a level that is a function of a ratio of the second resistance to a sum of the first and second resistances, and when the output signal is a second logic level, the reference signal has a level that is a function of a ratio of a sum of the second and third resistances to a sum of the first, second and third resistances.

6. The circuit of claim 3, wherein the control circuit comprises a transistor including a first source/drain terminal connected to the second end of the third resistor, a second source/drain terminal connecting to a third source providing a third voltage, and a gate terminal for receiving the first control signal, the first voltage being greater than the third voltage.

7. The circuit of claim 1, wherein the voltage clamp comprises at least first, second, third and fourth transistors, each transistor including first and second source/drain terminals and a gate terminal, the gate terminals of each of the transistors connecting to the second source, the first source/drain terminal of the first transistor receiving the reference signal, the second source/drain terminal of the first transistor being connected to the comparator, the first source/drain terminal of the second transistor being connected to a first node of the reference generator, the second source/drain terminal of the second transistor being connected to a first node of the hysteresis circuit, the first source/drain terminal of the third transistor being connected to a second node of the hysteresis circuit, the second source/drain terminal being connected to a second node of the reference generator, the first source/drain terminal of the fourth transistor being connected to the second node of the reference generator, and the second source/drain terminal of the fourth transistor being connected to the control circuit.

8. The circuit of claim 7, wherein each of the first, second, third and fourth transistors in the voltage clamp comprises an n-type metal-oxide semiconductor device.

9. The circuit of claim 1, wherein the control circuit comprises at least one transistor having a first source/drain terminal connected to the reference generator, a second source/drain terminal connecting to a third source providing a third voltage, the first voltage being greater than the third voltage, and a gate terminal for receiving the first control signal, the at least one transistor being turned off during the first mode of operation and being turned on during the second mode of operation.

10. The circuit of claim 9, wherein the at least one transistor in the control circuit comprises an n-type metal-oxide semiconductor device.

11. The circuit of claim 1, wherein the hysteresis circuit comprises a transistor including a first source/drain terminal connected to a first node of the reference generator, a second source/drain terminal connected to a second node of the reference generator, and a gate terminal for receiving a second control signal which is a function of the output signal of the comparator, the transistor electrically connecting the first and second nodes of the reference generator together when the output signal is a first level, and the transistor being turned off when the output signal is a second level.

12. The circuit of claim 11, wherein the second control signal comprises the output signal generated by the comparator.

13. The circuit of claim 1, wherein the first voltage is about five volts and the second voltage is about 3.3 volts.

14. The circuit of claim 1, wherein the comparator comprises control circuitry operative to selectively disable at least a portion of the comparator so as to reduce a power consumption of the comparator during the first mode of operation.

15. The circuit of claim 1, wherein the voltage clamp comprises at least first, second, third and fourth transistors, gate terminals of each of the first, second, third and fourth transistors connecting to a third source providing a third voltage, the first voltage being greater than the third voltage, a first source/drain terminal of the first transistor receiving the reference signal, a second source/drain terminal of the first transistor being connected to the comparator, a first source/drain terminal of the second transistor being connected to a first node of the reference generator, a second source/drain terminal of the second transistor being connected to a first node of the hysteresis circuit, a first source/drain terminal of the third transistor being connected to a second node of the hysteresis circuit, a second source/drain terminal being connected to a second node of the reference generator, a first source/drain terminal of the fourth transistor being connected to the second node of the reference generator, and a second source/drain terminal of the fourth transistor being connected to the control circuit.

16. An integrated circuit including at least one comparator circuit, the at least one comparator circuit comprising:

a reference generator connecting to a first source providing a first voltage, the reference generator being operative to generate a reference signal and including a control circuit selectively operable in one of at least a first mode and a second mode in response to a first control signal applied to the reference generator, wherein in the first mode the reference signal is not generated, and in the second mode the reference generator is operative to generate the reference signal;

a comparator connecting to a second source providing a second voltage, the second voltage being less than the first voltage, the comparator being operative to receive the reference signal and an input signal, and to generate an output signal which is a function of a comparison between the input signal and the reference signal;

a hysteresis circuit operative to selectively control a switching threshold of the comparator, relative to the input signal, as a function of the output signal of the comparator; and

a voltage clamp operative to limit a voltage applied to at least one of the control circuit, the comparator, and the hysteresis circuit to less than the second voltage.

17. The integrated circuit of claim 16, wherein the control circuit comprises at least one transistor having a first source/drain terminal connected to the reference generator, a second source/drain terminal connecting to a third source providing a third voltage, the first voltage being greater than the third voltage, and a gate terminal for receiving the first control signal, the transistor being turned off during the first mode of operation and being turned on during the second mode of operation.

18. The integrated circuit of claim 16, wherein the voltage clamp comprises at least first, second, third and fourth transistors, gate terminals of each of the first, second, third and fourth transistors connecting to a third source providing a third voltage, the first voltage being greater than the third voltage, a first source/drain terminal of the first transistor receiving the reference signal, a second source/drain terminal of the first transistor being connected to the comparator, a first source/drain terminal of the second transistor being connected to a first node of the reference generator, a second source/drain terminal of the second transistor being connected to a first node of the hysteresis circuit, a first source/drain terminal of the third transistor being connected to a second node of the hysteresis circuit, a second source/drain terminal being connected to a second node of the reference generator, a first source/drain terminal of the fourth transistor being connected to the second node of the reference generator, and a second source/drain terminal of the fourth transistor being connected to the control circuit.

19. The integrated circuit of claim 16, wherein the hysteresis circuit comprises a transistor including a first source/drain terminal connected to a first node of the reference generator, a second source/drain terminal connected to a second node of the reference generator, and a gate terminal for receiving a second control signal which is a function of the output signal of the comparator, the transistor electrically connecting the first and second nodes of the reference generator together when the output signal is a first level, and the transistor being turned off when the output signal is a second level.

20. The integrated circuit of claim 16, wherein the comparator comprises control circuitry operative to selectively disable at least a portion of the comparator so as to reduce a power consumption of the comparator during the first mode of operation.