High frequency switch circuit

• US 7,106,121 B2
• Filed: 04/08/2004
• Issued: 09/12/2006
• Est. Priority Date: 04/16/2003
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakatsuka, Tadayoshi, Hidaka, Kenichi, Tara, Katsushi
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): Nguyen, Hiep
• Application Number:
  US10/819,976
• Publication Number:
  US 20040207454A1
• Time in Patent Office: 887 Days
• Field of Search: 327/308, 333/81.R
• US Class Current: 327/308
• CPC Class Codes: H03J 2200/29 Self-calibration of a receiver
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors

Abstract

One end of each of five resistors is connected to each of the two ends and the respective intermediate points of a cascade of four depression-type FETs, while the other ends of the five resistors are provided with a predetermined voltage. This configuration fixes the source-drain potential of the four FETs. This fixing of the source-drain potential of the FETs permits stable application of a bias voltage for turning ON the FETs between the gate and the source each FET, so as to ensure the ON-OFF switching of the FETs.

Claims

1. A high frequency switch circuit, comprising:

a first FET, a second FET, a third FET, a fourth FET, a first high frequency signal input and output terminal, a second high frequency signal input and output terminal, first through ninth resistors, a first control terminal, and a second control terminal, wherein said first FET has a drain terminal connected to a source terminal of the second FET, a drain terminal of said second FET is connected to a source terminal of said third FET, a drain terminal of said third FET is connected to a source terminal of said fourth FET, a source terminal of said first FET is connected to said first high frequency signal input and output terminal, a drain terminal of said fourth FET is connected to said second high frequency signal input and output terminal, one end of said first resistor is connected to a gate terminal of said first FET, one end of said second resistor is connected to a gate terminal of said second FET, one end of said third resistor is connected to a gate terminal of said third FET, one end of said fourth resistor is connected to a gate terminal of said fourth FET, the other ends of said first through fourth resistors are connected in common to said first control terminal, one end of said fifth resistor is connected to said first high frequency signal input and output terminal, one end of said sixth resistor is connected to a connection point between said first FET and said second FET, one end of said seventh resistor is connected to a connection point between said second FET and said third FET, one end of said eighth resistor is connected to a connection point between said third FET and said fourth FET, one end of said ninth resistor is connected to said second high frequency signal input and output terminal, the other ends of said fifth through ninth resistors are connected in common to said second control terminal, a high level voltage or a low level voltage is selectively applied to said first control terminal, and a predetermined voltage is applied to said second control terminal, and wherein a third control terminal is connected to a voltage input terminal of a step-up circuit;

a voltage output terminal of said stepup circuit is connected to said second control terminal;

a voltage output terminal of said step-up circuit is connected to a supply voltage terminal of a logic circuit;

a fourth control terminal is connected to a signal input terminal of said logic circuit; and

a signal output terminal of said logic circuit is connected to said first control terminal.

2. A high frequency switch circuit, comprising:

a first FET, a second FET, a third FET, a fourth FET, a first high frequency signal input and output terminal, a second high frequency signal input and output terminal, first through ninth resistors, a first control terminal, and a second control terminal, wherein said first FET has a drain terminal connected to a source terminal of the second FET, a drain terminal of said second FET is connected to a source terminal of said third FET, a drain terminal of said third FET is connected to a source terminal of said fourth FET, a source terminal of said first FET is connected to said first high frequency signal input and output terminal, a drain terminal of said fourth FET is connected to said second high frequency signal input and output terminal, one end of said first resistor is connected to a gate terminal of said first FET, one end of said second resistor is connected to a gate terminal of said second FET, one end of said third resistor is connected to a gate terminal of said third FET, one end of said fourth resistor is connected to a gate terminal of said fourth FET, the other ends of said first through fourth resistors are connected in common to said first control terminal, one end of said fifth resistor is connected to said first high frequency signal input and output terminal, one end of said sixth resistor is connected to a connection point between said first FET and said second FET, one end of said seventh resistor is connected to a connection point between said second FET and said third FET, one end of said eighth resistor is connected to a connection point between said third FET and said fourth FET, one end of said ninth resistor is connected to said second high frequency signal input and output terminal, the other ends of said fifth through ninth resistors are connected in common to said second control terminal, a high level voltage or a low level voltage is selectively applied to said first control terminal, and a predetermined voltage is applied to said second control terminal, and wherein a third control terminal is connected to a voltage input terminal of a step-up circuit;

a voltage output terminal of said stepup circuit is connected-to the anode of a diode;

the cathode of said diode is connected to said second control terminal;

a voltage output terminal of said step-up circuit is connected to a supply voltage terminal of a logic circuit;

a fourth control terminal is connected to a signal input terminal of said logic circuit; and

a signal output terminal of said logic circuit is connected to said first control terminal.

3. A high frequency switch circuit, comprising:

a first FET, a second FET, a third FET, a fourth FET, a first high frequency signal input and output terminal, a second high frequency signal input and output terminal, first through ninth resistors, a first control terminal, and a second control terminal, wherein said first FET has a drain terminal connected to a source terminal of the second FET, a drain terminal of said second FET is connected to a source terminal of said third FET, a drain terminal of said third FET is connected to a source terminal of said fourth FET, a source terminal of said first FET is connected to said first high frequency signal input and output terminal, a drain terminal of said fourth FET is connected to said second high frequency signal input and output terminal, one end of said first resistor is connected to a gate terminal of said first FET, one end of said second resistor is connected to a gate terminal of said second FET, one end of said third resistor is connected to a gate terminal of said third FET, one end of said fourth resistor is connected to a gate terminal of said fourth FET, the other ends of said first through fourth resistors are connected in common to said first control terminal, one end of said fifth resistor is connected to said first high frequency signal input and output terminal, one end of said sixth resistor is connected to a connection point between said first FET and said second FET, one end of said seventh resistor is connected to a connection point between said second FET and said third FET, one end of said eighth resistor is connected to a connection point between said third FET and said fourth FET, one end of said ninth resistor is connected to said second high frequency signal input and output terminal, the other ends of said fifth through ninth resistors are connected in common to said second control terminal, a high level voltage or a low level voltage is selectively applied to said first control terminal, and a predetermined voltage is applied to said second control terminal, and wherein a third control terminal is connected to a voltage input terminal of a step-up circuit;

a voltage output terminal of said stepup circuit is connected to one voltage input terminal of a voltage selection circuit;

said third control terminal is connected to the other voltage input terminal of said voltage selection circuit;

a voltage output terminal of said voltage selection circuit is connected to said second control terminal;

a voltage output terminal of said step-up circuit is connected to a supply voltage terminal of a logic circuit;

a fourth control terminal is connected to a signal input terminal of said logic circuit;

a signal output terminal of said logic circuit is connected to said first control terminal; and

said fourth control terminal is connected to a switching control terminal of said voltage selection circuit;

whereby when a control signal for turning OFF said first through fourth FETs is provided to said fourth control terminal, said voltage selection circuit selects the voltage of said third control terminal, while when a control signal for turning ON said first through fourth FETs is provided to said fourth control terminal, said voltage selection circuit selects the output voltage of said step-up circuit.

4. A high frequency switch circuit, comprising:

a first FET, a second FET, a third FET, a fourth FET, a first high frequency signal input and output terminal, a second high frequency signal input and output terminal, first through ninth resistors, a first control terminal, and a second control terminal, wherein said first FET has a drain terminal connected to a source terminal of the second FET, a drain terminal of said second FET is connected to a source terminal of said third FET, a drain terminal of said third FET is connected to a source terminal of said fourth FET, a source terminal of said first FET is connected to said first high frequency signal input and output terminal, a drain terminal of said fourth FET is connected to said second high frequency signal input and output terminal, one end of said first resistor is connected to a gate terminal of said first FET, one end of said second resistor is connected to a gate terminal of said second FET, one end of said third resistor is connected to a gate terminal of said third FET, one end of said fourth resistor is connected to a gate terminal of said fourth FET, the other ends of said first through fourth resistors are connected in common to said first control terminal, one end of said fifth resistor is connected to said first high frequency signal input and output terminal, one end of said sixth resistor is connected to a connection point between said first FET and said second FET, one end of said seventh resistor is connected to a connection point between said second FET and said third FET, one end of said eighth resistor is connected to a connection point between said third FET and said fourth FET, one end of said ninth resistor is connected to said second high frequency signal input and output terminal, the other ends of said fifth through ninth resistors are connected in common to said second control terminal, a high level voltage or a low level voltage is selectively applied to said first control terminal, and a predetermined voltage is applied to said second control terminal, and wherein a third control terminal is connected to a voltage input terminal of a step-up circuit;

a voltage output terminal of said stepup circuit is connected to one voltage input terminal of a voltage selection circuit;

said third control terminal is connected to the other voltage input terminal of said voltage selection circuit;

a voltage output terminal of said voltage selection circuit is connected to the anode of a diode;

the cathode of said diode is connected to said second control terminal;

a voltage output terminal of said step-up circuit is connected to a supply voltage terminal of a logic circuit;

a fourth control terminal is connected to a signal input terminal of said logic circuit;

a signal output terminal of said logic circuit is connected to said first control terminal; and

said fourth control terminal is connected to a switching control terminal of said voltage selection circuit;

whereby when a control signal for turning OFF said first through fourth FETs is provided to said fourth control terminal, said voltage selection circuit selects the voltage of said third control terminal, while when a control signal for turning ON said first through fourth FETs is provided to said fourth control terminal, said voltage selection circuit selects the output voltage of said step-up circuit.

5. A high frequency switch circuit, comprising:

a first FET, a second FET, a third FET, a fourth FET, a first high frequency signal input and output terminal, a second high frequency signal input and output terminal, first through ninth resistors, a first control terminal, and a second control terminal, wherein said first FET has a drain terminal connected to a source terminal of the second FET, a drain terminal of said second FET is connected to a source terminal of said third FET, a drain terminal of said third FET is connected to a source terminal of said fourth FET, a source terminal of said first FET is connected to said first high frequency signal input and output terminal, a drain terminal of said fourth FET is connected to said second high frequency signal input and output terminal, one end of said first resistor is connected to a gate terminal of said first FET, one end of said second resistor is connected to a gate terminal of said second FET, one end of said third resistor is connected to a gate terminal of said third FET, one end of said fourth resistor is connected to a gate terminal of said fourth FET, the other ends of said first through fourth resistors are connected in common to said first control terminal, one end of said fifth resistor is connected to said first high frequency signal input and output terminal, one end of said sixth resistor is connected to a connection point between said first FET and said second FET, one end of said seventh resistor is connected to a connection point between said second FET and said third FET, one end of said eighth resistor is connected to a connection point between said third FET and said fourth FET, one end of said ninth resistor is connected to said second high frequency signal input and output terminal, the other ends of said fifth through ninth resistors are connected in common to said second control terminal, a high level voltage or a low level voltage is selectively applied to said first control terminal, and a predetermined voltage is applied to said second control terminal, and wherein the resistance values of said fifth through ninth resistors are 1 kΩ

or higher.