Word line arrangement having multi-layer word line segments for three-dimensional memory array

• US 7,106,652 B2
• Filed: 04/11/2005
• Issued: 09/12/2006
• Est. Priority Date: 03/31/2003
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US11/103,249
• Publication Number:
  US 20050180248A1
• Time in Patent Office: 519 Days
• Field of Search: None
• US Class Current: 365/230.06
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.

Claims

1. An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line traversing perpendicular to the word line segments.

2. The integrated circuit of claim 1 further comprising at least three word line layers, wherein at least some segmented word lines comprise connected-together word line segments on a first group of one or more word line layers, and at least some segmented word lines comprise connected-together word line segments on a second group of one or more word line layers.

3. The integrated circuit of claim 1 further comprising a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

4. The integrated circuit of claim 3 wherein each select node traverses across at least a portion of the array on an interconnect layer disposed beneath the memory array.

5. The integrated circuit of claim 1 wherein all word line segments for each respective word line are connected together by a respective single vertical connection.

6. The integrated circuit of claim 5 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array.

7. The integrated circuit of claim 5 wherein the word line segments in each array block are interleaved.

8. The integrated circuit of claim 7 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

9. The integrated circuit of claim 5 wherein the array is configured to simultaneously program a group of at least two memory cells associated with a single word line.

10. The integrated circuit of claim 9 wherein at most one memory cell of a simultaneously programmed group of memory cells is associated with an individual word line segment.

11. The integrated circuit of claim 9 wherein each word line, when selected for programming, is driven by an N-channel transistor to a selected programming bias level.

12. The integrated circuit of claim 1 wherein:

the memory array is organized as a plurality of blocks;

each block includes a respective plurality of N selected bias lines; and

the integrated circuit further comprises a multi-headed word line decoder circuit having a plurality of select nodes, each select node being coupled to a respective group of N word line driver circuits associated with a block, each coupled to a respective one of the N selected bias lines.

13. The integrated circuit of claim 12 wherein each respective selected bias line is operably driven to a selected bias level by a respective first circuit arranged to initially drive the line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

14. The integrated circuit of claim 13 wherein the respective second circuit for each respective selected bias line comprises a plurality of spatially distributed circuits operably coupling the respective selected bias line to a source of the selected bias level.

15. The integrated circuit of claim 13 wherein a given memory block includes an unselected bias line shared by all word line driver circuits associated with the given memory block.

16. The integrated circuit of claim 1 comprising antifuse memory cells.

17. A computer readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 1.

18. A method for programming a three-dimensional passive element memory cell array, said method comprising the steps of:

selecting a block of the memory array, each block comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each block further including a respective plurality of N selected bias lines traversing perpendicular to the word line segments;

selecting one of a plurality of select nodes of a multi-headed word line decoder circuit, each select node being coupled to a respective group of N word line driver circuits associated with the selected block, each word line driver circuit coupled to a respective one of the N selected bias lines for the selected block;

driving one of the N selected bias lines for the selected block to a selected bias level, thereby coupling a selected word line to a source of a suitable programming bias level; and

coupling a selected bit line in the selected block to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby program a selected memory cell coupled between the selected bit line and the selected word line.

19. The method as recited in claim 18 wherein said one of the N selected bias lines is driven by a first circuit arranged to initially drive the bias line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

20. The method as recited in claim 18 further comprising coupling a second selected bit line in the selected block to either a suitable programming bias level or an inhibit bias level in accordance with a respective data bit to be programmed, to thereby program a second selected memory cell coupled between the second selected bit line and the selected word line.

21. An integrated circuit comprising a three-dimensional passive element memory cell array, said memory array comprising a plurality of segmented word lines, each word line comprising at least one word line segment on each of at least two word line layers that are connected together, each word line being operably coupled to an associated selected bias line by a multi-headed decoder circuit, said decoder circuit comprising a plurality of select nodes routed on a layer beneath the memory array and coupled to a respective group of at least one word line driver circuit for each respective one of at least three blocks of the array.

22. The integrated circuit of claim 21 further comprising at least three word line layers, wherein at least some segmented word lines comprise connected-together word line segments on a first group of one or more word line layers, and at least some segmented word lines comprise connected-together word line segments on a second group of one or more word line layers.

23. The integrated circuit of claim 21 wherein the memory array comprises memory cells respectively formed between a word line segment disposed on a word line layer and respective bit lines disposed on each of at least one associated bit line layer, each bit line layer being associated with at most one word line layer.

24. The integrated circuit of claim 21 wherein all word line segments for each respective word line are connected together by a respective single vertical connection.

25. The integrated circuit of claim 24 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array.

26. The integrated circuit of claim 24 wherein the word line segments on a given word line layer in each array block are interleaved.

27. The integrated circuit of claim 26 comprising word lines including a respective word line segment in each of two adjacent blocks of the memory array which share a vertical connection.

28. The integrated circuit of claim 21 wherein:

each memory array block includes a respective plurality of N selected bias lines; and

each select node of the multi-headed word line decoder circuit is coupled to a respective group of N word line driver circuits associated with a block, each coupled to a respective one of the N selected bias lines.

29. The integrated circuit of claim 28 wherein N=>

1.

30. The integrated circuit of claim 29 wherein N=>

2.

31. The integrated circuit of claim 30 wherein N=4.

32. The integrated circuit of claim 28 wherein each respective selected bias line is operably driven to a selected bias level by a respective first circuit arranged to initially drive the line from an unselected bias level toward the selected bias level, and by a second circuit for subsequently providing a lower impedance path to the selected bias level.

33. The integrated circuit of claim 32 wherein the respective second circuit for each respective selected bias line comprises a plurality of spatially distributed circuits operably coupling the respective selected bias line to a source of the selected bias level.

34. The integrated circuit of claim 28 wherein each memory block includes an unselected bias line shared by all word line driver circuits associated with the block.

35. The integrated circuit of claim 21 comprising antifuse memory cells.

36. A computer readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 21.