Method for controlling semiconductor processing apparatus

• US 7,107,115 B2
• Filed: 01/26/2006
• Issued: 09/12/2006
• Est. Priority Date: 03/04/2003
• Status: Active Grant

• Current Assignee: Hitachi High-Tech Company Limited (Hitachi, Ltd.)
• Original Assignee: Hitachi High-Technologies Corporation (Hitachi, Ltd.)
• Inventors: Tanaka, Junichi, Ikuhara, Shoji, Yamamoto, Hideyuki, Kagoshima, Akira
• Primary Examiner(s): Picard, Leo
• Assistant Examiner(s): Kosowski, Alexander
• Application Number:
  US11/339,712
• Publication Number:
  US 20060129264A1
• Time in Patent Office: 229 Days
• Field of Search: 700109-110, 700/121, 438/7, 438/9, 438/14, 438/16, 438/905
• US Class Current: 700/109
• CPC Class Codes: H01L 21/67028 for cleaning followed by drying, rinsing, stripping, blasting or the like
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/67253 Process monitoring, e.g. flow or thickness monitoring
• CPC Class Codes: Y10S 438/905 Cleaning of reaction chamber

Abstract

Occurrence of a process abnormality in a semiconductor processing apparatus is obtained by obtaining an index of a processing size of each of wafers within an X-th lot, in which the X represents an integer, based on data obtained during processing of each of the wafers of the X-th lot, obtaining an index of a processing size of each of wafers within an X+1-th lot, based on data thereof and anticipating an index of a processing sizes of each of wafers within an X+2-th lot, based on the index obtained as to each of the wafers of the X-th lot and the X+1-th lot. A process abnormality occurring during the processing of a wafer of the X+2-th lot is anticipated when the anticipated index of the X+2-th lot exceeds an allowance range.

Claims

1. A method of anticipating occurrence of a process abnormality in a semiconductor processing apparatus for processing wafers, comprising the steps of:

obtaining an index of a processing size of each of wafers within an X-th lot, in which the X represents an integer, based on data from one of a sensor disposed in the semiconductor processing apparatus and a measuring instrument for measuring a processing result of a semiconductor device, which is obtained during a processing of each of the wafers contained within the X-th lot;

obtaining an index of a processing size of each of wafers within an X+1-th lot, which is a next lot to be processed after the X-th lot, based on data from one of the sensor disposed in the semiconductor processing apparatus and from the measuring instrument for measuring a processing result of a semiconductor device, which is obtained during a processing of each of the wafers contained within the X+1-th lot;

anticipating an index of a processing size of each of wafers within an X+2-th lot, which is a next lot to be processed after the X+1-th lot, based on the index obtained as to each of the wafers within the X-th lot and the index obtained as to each of the wafers within the X+1-th lot; and

anticipating that a process abnormality occurs during the processing of at least one of the wafers within the X+2-th lot when the anticipated index of the at least one of the wafers within the X+2-th lot exceeds an allowance range.

2. A method of anticipating occurrence of a process abnormality in a semiconductor processing apparatus for processing wafers, comprising the steps of:

obtaining a mean value of indices of processing sizes of respective wafers within an X-th lot, in which X represents an integer, based on the data from one of a sensor disposed in the semiconductor processing apparatus and a measuring instrument for measuring a processing result of a semiconductor device, which is obtained during a processing of each of the wafers contained within the X-th lot;

obtaining a mean value of indices of processing sizes of respective wafers within an X+1-th lot, which is a next lot to be processed after the X-th lot, based on data from one of the sensor disposed in the semiconductor processing apparatus and the measuring instrument for measuring a processing result of a semiconductor device, which is obtained during a processing of each of the wafers contained within the X+1-th lot;

obtaining a difference between the mean value of indices of processing sizes of respective wafers within the X-th lot and the mean value of indices of processing sizes of respective wafers within the X+1-th lot, adding the difference to each of the indices of processing sizes of respective wafers within the X+1-th lot, thereby to anticipate an index of a processing size of each of wafers within an X+2-th lot, which is a next lot to be processed after the X+1-th lot; and

anticipating that a process abnormality occurs during the processing of at least one of the wafers within the X+2-th lot when the anticipated index of the at least one of the wafers within the X+2-th lot exceeds an allowance range.