Method and system for multi-channel transfer of data and control information

• US 7,107,383 B1
• Filed: 05/03/2000
• Issued: 09/12/2006
• Est. Priority Date: 05/03/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rajan, Sundar
• Primary Examiner(s): Revak, Christopher
• Assistant Examiner(s): LAFORGIA, CHRISTIAN A
• Application Number:
  US09/564,592
• Time in Patent Office: 2,323 Days
• Field of Search: 370/395, 380/235, 382/232, 710/52, 710/300, 710/305, 710/310, 710/306, 710/311, 710/314, 710/315
• US Class Current: 710/306
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/14 Multichannel or multilink protocols
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.

Claims

1. A system for transferring data in a multi-channel, point-to-point environment, the system comprising:

a plurality of processing chips connected to a bridge bus;

a bridge connected to the bridge bus and to a system bus;

a plurality of buffers coupled to the bridge, each buffer being assigned to a respective processing chip; and

a first memory connected to the bridge, the first memory storing cells that are exchanged between the bridge bus and the system bus, each cell including an address for the at least one processing chip, wherein the bridge places a cell destined for a destination processing chip in the respective buffer assigned to the destination processing chip and wherein the bridge places a cell received from an initiating processing chip in a location assigned to the initiating processing chip in a second memory coupled to the system bus.

2. The system of claim 1 wherein the bridge comprises:

a system bus interface connected to the system bus;

a memory interface connected to the system bus interface;

a cell initiated serial interface connected to the memory interface and to the bridge bus; and

a control logic connected to the system bus interface, the memory interface, and the cell initiated serial interface.

3. The bridge of claim 2 wherein the system bus interface further comprises a first-in first-out (FIFO) stack for storing write-postings of data cells.

4. The bridge of claim 2 wherein the cell initiated serial interface generates null cells for transfer to the bridge bus.

5. The bridge of claim 2 wherein the cell initiated serial interface removes null cells received from the bridge bus.

6. The system of claim 1, wherein the bridge bus has a first data transfer protocol and the system bus has a second data transfer protocol, and wherein the first data transfer protocol and the second data transfer protocol are different data transfer protocols.

7. A bridge for transferring data in a multi-channel, point-to-point environment, the bridge comprising:

a system bus interface connected to a system bus;

a memory interface connected to the system bus interface and to a memory, wherein the memory stores cells that are transmitted over the point-to-point environment, each cell including an address for the at least one processing chip;

a cell initiated serial interface connected to the memory interface and to a bridge bus; and

a control logic connected to the system bus interface, the memory interface, and the cell initiated serial interface, wherein the control logic places a cell destined for a destination processing chip in a respective buffer assigned to a destination processing chip, and places a cell received from an initiating processing chip in a second respective buffer assigned to the initiating processing chip.

8. The bridge of claim 7 wherein the system bus interface further comprises a first-in first-out (FIFO) stack for storing write-postings of data cells.

9. The bridge of claim 7 wherein the cell initiated serial interface generates null cells for transfer to the bridge bus.

10. The bridge of claim 7 wherein the cell initiated serial interface removes null cells received from the bridge bus.

11. The bridge of claim 7, wherein the bridge bus has a first data transfer protocol and the system bus has a second data transfer protocol, and wherein the first data transfer protocol and the second data transfer protocol are different data transfer protocols.

12. A method of transmitting data in a multi-channel, point-to-point environment, the method comprising:

transmitting a cell to a first bus;

selecting a memory queue from a plurality of memory queues in which to place the cell, wherein each memory queue is assigned to a respective of a plurality of processing chips;

writing the cell to the selected memory queue;

placing the cell within a bridge buffer; and

bursting the cell to a respective processing chip corresponding to the bridge buffer via a second bus;

receiving a second cell from a respective processing chip; and

placing the received cell in a second memory location coupled to the first bus and assigned to the respective processing chip.

13. The method of claim 12 wherein a cell is a data cell or a control cell.

14. The method of claim 12 further comprising:

inserting a null cell if no data is transmitted for a channel.

15. The method of claim 12 wherein the cell of data is fixed in size.

16. The method of claim 12 further comprising:

allocating a queue per channel.

17. The method of claim 16 further comprising:

allocating a queue for data cells; and

allocating a queue for control cells.

18. The method of claim 12 wherein cells are continuously burst to the appropriate processing chip.

19. The method of claim 12 wherein timeslots are allocated on a channel-by-channel basis.

20. A method of receiving data in a multi-channel, point-to-point environment, the method comprising:

receiving a cell by a first bus coupled to a plurality of processing chips;

determining a receiving queue from a plurality of queues in which to place the cell;

placing the cell within a bridge buffer;

saving the cell into the queue;

fetching a descriptor corresponding to the cell;

bursting the cell to a bus interface that corresponds to the appropriate processing chip;

receiving the cell on a system bus; and

placing the cell in a location corresponding to the descriptor in a memory coupled to the system bus.

21. The method of claim 20 wherein a cell is a data cell or a control cell.

22. The method of claim 20 further comprising:

removing null data cells.

23. The method of claim 20 wherein the cell of data is fixed in size.

24. The method of claim 20 further comprising:

allocating a queue per channel.

25. The method of claim 24 further comprising:

allocating a queue for data cells; and

allocating a queue for control cells.

26. The method of claim 20 wherein cells are continuously received.

27. The method of claim 20 wherein timeslots are allocated on a channel-by-channel basis.

28. A system for transmitting data in a multi-channel, point-to-point environment, the system comprising:

means for transmitting a cell to a first bus;

means for selecting a memory queue from a plurality of memory queues in which to place the cell, wherein each memory queue is assigned to a respective of a plurality of processing chips;

means for writing the cell to the selected memory queue;

means for placing the cell within a bridge buffer; and

means for bursting the cell to the respective processing chip corresponding to the bridge buffer via a second bus;

receiving a second cell from a respective processing chip; and

placing the received cell in a second memory location coupled to the first bus and assigned to the respective processing chip.

29. A system for receiving data in a multi-channel, point-to-point environment, the system comprising:

means for receiving a cell by a first bus coupled to a plurality of processing chips;

means for determining a receiving queue from a plurality of queues in which to place the cell;

means for placing the cell within a bridge buffer;

means for saving the cell into the queue;

means for fetching a descriptor corresponding to the cell;

means for bursting the cell to a bus interface that corresponds to the appropriate processing chip;

means for receiving the cell on a system bus; and

means for placing the cell in a location corresponding to the descriptor in a memory coupled to the system bus.

30. A computer readable medium comprising instructions, which when executed on a processor, perform a method for transmitting data in a multi-channel, point-to-point environment, comprising:

transmitting a cell to a first bus;

selecting a memory queue from a plurality of memory queues in which to place the cell, wherein each memory queue is assigned to a respective of a plurality of processing chips;

writing the cell to the selected memory queue;

placing the cell within a bridge buffer; and

bursting the cell to a respective processing chip corresponding to the bridge buffer via a second bus;

receiving a second cell from a respective processing chip; and

placing the received cell in a second memory location coupled to the first bus and assigned to the respective processing chip.

31. A computer readable medium comprising instructions, which when executed on a processor, perform a method receiving data in a multi-channel, point-to-point environment, comprising:

receiving a cell by a first bus coupled to a plurality of processing chips;

determining a receiving queue from a plurality of queues in which to place the cell;

placing the cell within a bridge buffer;

saving the cell into the queue;

fetching a descriptor corresponding to the cell;

bursting the cell to a bus interface that corresponds to the appropriate processing chip;

receiving the cell on a system bus; and

placing the cell in a location corresponding to the descriptor in a memory coupled to the system bus.