System and method for preventing data corruption in solid-state memory devices after a power failure

• US 7,107,480 B1
• Filed: 12/20/2001
• Issued: 09/12/2006
• Est. Priority Date: 12/22/2000
• Status: Expired due to Term

• Current Assignee: Innovative Memory Systems, Inc. (Wi-LAN Inc.)
• Original Assignee: Simpletech, Inc. (Western Digital Corporation)
• Inventors: Robinson, Brian H., Moshayedi, Mark
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US10/032,332
• Time in Patent Office: 1,727 Days
• Field of Search: 714/2, 714/3, 714/5, 714/6, 714/8, 714/13, 714/18, 714/42, 714/47, 714/14
• US Class Current: 714/2
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30

Abstract

A data preservation system for flash memory systems with a host system, the flash memory system receiving a host system power supply and energizing an auxiliary energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to continue write operations to flash memory.

Claims

1. A data preservation system for flash memory systems connected with a host system, the flash memory system receiving a host system power supply and energizing a supplemental energy store therewith and communicating with the host system via an interface bus, wherein, upon loss of the host system power supply, the flash memory system actively isolates the connection to the host system power supply and isolates the interface bus and employs the supplemental energy store to complete pending flash memory write operations.

2. A data preservation system for flash memory systems receiving a power supply and experiencing power failure thereof, the data preservation system comprising:

a detection circuit in communication with the power supply;

an auxiliary power source;

an isolation circuit for isolating the auxiliary power source upon detection of a power failure by the detection circuit; and

controller circuitry configured to complete pending flash memory write operations storing data from volatile memory into flash memory using the auxiliary power source.

3. The data preservation system of claim 2, wherein the volatile memory comprises a tri-state buffer.

4. The data preservation system of claim 2, wherein the detection circuit comprises a voltage detector.

5. The data preservation system of claim 2, wherein the auxiliary power source comprises capacitors.

6. A method of preserving data in flash memory systems experiencing a power failure, the method comprising:

charging an auxiliary power source with a supply voltage;

detecting a loss of power of the supply voltage;

isolating the auxiliary power source; and

utilizing the auxiliary power source to complete pending flash memory write operations storing data stored in volatile memory into flash memory.

7. The method of claim 6, wherein isolating the auxiliary power source comprises opening a relay interconnecting the supply voltage and the auxiliary power source.

8. The method of claim 6, further comprising isolating a host system data bus from the flash memory system.

9. A data preservation system comprising:

a power detector;

an auxiliary power source;

an isolator adapted to isolate the auxiliary power source when the power detector detects a loss of power; and

a data store configured to complete pending operations storing data into non-volatile memory powered by the auxiliary power source when the power detector detects a loss of power,

wherein the operations storing data into the non-volatile memory are pending prior to the loss of power.

10. The system of claim 9, wherein the non-volatile memory comprises flash memory.

11. A method for storing data in a memory device, the method comprising:

detecting a power reduction;

decoupling an auxiliary power source upon detecting a power reduction; and

completing pending operations storing data into non-volatile memory using the auxiliary power source,

wherein the operations storing data into the non-volatile memory are pending prior to detecting the power reduction.

12. The method of claim 11, further comprising decoupling a volatile memory from external connections.

13. The method of claim 12, wherein the pending operations are storing data from the volatile memory into the non-volatile memory.

14. A memory device comprising:

means for detecting loss of power;

means for providing auxiliary power;

means for isolating the memory device upon detection of loss of power; and

means for completing pending operations storing data into non-volatile memory utilizing the auxiliary power,

wherein the operations storing data into the non-volatile memory are pending prior to detecting the loss of power.