Fault tolerant sleep mode of operation

• US 7,107,487 B2
• Filed: 04/12/2002
• Issued: 09/12/2006
• Est. Priority Date: 04/12/2002
• Status: Active Grant

• Current Assignee: Lenovo PC International Limited (Lenovo Group Ltd.)
• Original Assignee: Lenovo Singapore Pte Limited (Lenovo Group Ltd.)
• Inventors: Ahmad, Nazir Haroon, Aklilu, Ameha, Kern, Eric Richard, Hoff, James Patrick, Dayan, Richard Alan, Chin, Jordan Hsiao Ping
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): DUNCAN, MARC M
• Application Number:
  US10/122,251
• Publication Number:
  US 20030196137A1
• Time in Patent Office: 1,614 Days
• Field of Search: 714/24, 714/21, 714/15
• US Class Current: 714/24
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: H04W 52/0225 using monitoring of external events, e.g. the presence of a signal
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A method, system and computer program product for implementing a fault tolerant sleep mode of operation. The system state information may be stored in a volatile memory and in a non-volatile storage unit prior to entering the sleep mode of operation. If a memory corruption event, e.g., power outage, brownout, power surge, occurs during the sleep mode of operation, then, upon receiving an invocation to resume to a normal mode of operation, the system state information stored in the non-volatile storage unit may be reloaded into the volatile memory. By reloading the system state information stored in the non-volatile storage into the volatile memory, the computer system may resume to a normal mode of operation from a sleep mode of operation without any corruption or loss of data.

Claims

1. A method for implementing a fault tolerant sleep mode of operation comprising the steps of:

storing system state information and a value used to verify integrity of said system state information in a volatile memory;

storing a copy of said system state information and said value used to verify integrity of said system state information in a non-volatile storage unit;

entering said sleep mode of operation;

receiving an indication to enter a normal mode of operation; and

determining if integrity of said system state information stored in said volatile memory is maintained, wherein if said integrity of at least a portion of said system state information in said volatile memory is not maintained then the method further comprises the step of;

reloading at least said portion of said system state information stored in said non-volatile storage unit into said volatile memory.

2. The method as recited in claim 1, wherein if said integrity of at least a portion of said system state information in said volatile memory is not maintained then the method further comprises the step of:

entering said normal mode of operation using said reloaded system state information stored in said volatile memory.

3. The method as recited in claim 1, wherein if said integrity of said system state information in said volatile memory is maintained then the method further comprises the step of:

entering said normal mode of operation using said system state information stored in said volatile memory.

4. The method as recited in claim 1, wherein integrity of said system state information stored in said volatile memory is determined by performing a hash function on said system state information stored in said volatile memory and comparing a value produced by said hash function with said value stored in said volatile memory.

5. The method as recited in claim 1, wherein integrity of said system state information stored in said volatile memory is determined by performing a checksum function on said system state information stored in said volatile memory and comparing a value produced by said checksum function with said value stored in said volatile memory.

6. A computer program product embodied in a machine readable medium for implementing a fault tolerant sleep mode of operation comprising the programming steps of:

storing system state information and a value used to verify integrity of said system state information in a volatile memory;

storing a copy of said system state information and said value used to verify integrity of said system state information in a non-volatile storage unit;

entering said sleep mode of operation;

receiving an indication to enter a normal mode of operation; and

determining if integrity of said system state information stored in said volatile memory is maintained, wherein if said integrity of at least a portion of said system state information in said volatile memory is not maintained then the method further comprises the step of;

reloading at least a portion of said system state information stored in said non-volatile storage unit into said volatile memory.

7. The computer program product as recited in claim 6, wherein if said integrity of at least a portion of said system state information in said volatile memory is not maintained then the computer program product further comprises the programming step of:

entering said normal mode of operation using said reloaded system state information stored in said volatile memory.

8. The computer program product as recited in claim 6, wherein if said integrity of said system state information in said volatile memory is maintained then the computer program product further comprises the programming step of:

entering said normal mode of operation using said system state information stored in said volatile memory.

9. The computer program product as recited in claim 6, wherein integrity of said system state information stored in said volatile memory is determined by performing a hash function on said system state information stored in said volatile memory and comparing a value produced by said hash function with said value stored in said volatile memory.

10. The computer program product as recited in claim 6, wherein integrity of said system state information stored in said volatile memory is determined by performing a checksum function on said system state information stored in said volatile memory and comparing a value produced by said checksum function with said value stored in said volatile memory.

11. A system, comprising:

a memory unit operable for storing a computer program operable for implementing a fault tolerant sleep mode of operation; and

a processor coupled to said memory unit, wherein said processor, responsive to said computer program, comprises;

circuitry operable for storing system state information and a value used to verify integrity of said system state information in a volatile memory;

circuitry operable for storing a copy of said system state information and said value used to verify integrity of said system state information in a non-volatile storage unit;

circuitry operable for entering said sleep mode of operation;

circuitry operable for receiving an indication to enter a normal mode of operation; and

circuitry operable for determining if integrity of said system state information stored in said volatile memory is maintained, wherein if said integrity of at least a portion of said system state information in said volatile memory is not maintained then said processor further comprises;

circuitry operable for reloading at least a portion of said system state information stored in said non-volatile storage unit into said volatile memory.

12. The system as recited in claim 11, wherein if said integrity of at least a portion of said system state information in said volatile memory is not maintained then said processor further comprises:

circuitry operable for entering said normal mode of operation using said reloaded system state information stored in said volatile memory.

13. The system as recited in claim 11, wherein if said integrity of said system state information in said volatile memory is maintained then said processor further comprises:

circuitry operable for entering said normal mode of operation using said system state information stored in said volatile memory.

14. The system as recited in claim 11, wherein integrity of said system state information stored in said volatile memory is determined by performing a hash function on said system state information stored in said volatile memory and comparing a value produced by said hash function with said value stored in said volatile memory.

15. The system as recited in claim 11, wherein integrity of said system state information stored in said volatile memory is determined by performing a checksum function on said system state information stored in said volatile memory and comparing a value produced by said checksum function with said value stored in said volatile memory.

16. A system, comprising:

means for storing system state information and a value used to verify integrity of said system state information in a volatile memory;

means for storing a copy of said system state information and said value used to verify integrity of said system state information in a non-volatile storage unit;

means for entering said sleep mode of operation;

means for receiving an indication to enter a normal mode of operation; and

means for determining if integrity of said system state information stored in said volatile memory is maintained, wherein if said integrity of at least a portion of said system state information in said volatile memory is not maintained then the system further comprises;

means for reloading at least a portion of said system state information stored in said non-volatile storage unit into said volatile memory.

17. The system as recited in claim 16, wherein if said integrity of at least a portion of said system state information in said volatile memory is not maintained then the system further comprises:

means for entering said normal mode of operation using said reloaded system state information stored in said volatile memory.

18. The system as recited in claim 16, wherein if said integrity of said system state information in said volatile memory is maintained then the system further comprises:

means for entering said normal mode of operation using said system state information stored in said volatile memory.

19. The system as recited in claim 16, wherein integrity of said system state information stored in said volatile memory is determined by performing a hash function on said system state information stored in said volatile memory and comparing a value produced by said hash function with said value stored in said volatile memory.

20. The system as recited in claim 16, wherein integrity of said system state information stored in said volatile memory is determined by performing a checksum function on said system state information stored in said volatile memory and comparing a value produced by said checksum function with said value stored in said volatile memory.