Diagnostic method for detection of multiple defects in a Level Sensitive Scan Design (LSSD)

• US 7,107,502 B2
• Filed: 01/29/2004
• Issued: 09/12/2006
• Est. Priority Date: 01/29/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Burdine, Todd Michael
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US10/767,046
• Publication Number:
  US 20050172188A1
• Time in Patent Office: 957 Days
• Field of Search: None
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence

Abstract

Examiner'"'"'s permission under MPEP §608.01(q) and 37 CFR §1.125(b) is requested to submit a substitute specification and abstract. The substitute specification corrects typographical errors, grammar and formatting. No new matter has been added. The substitute specification and abstract contain no new matter to the specification of record. A marked-up version is attached along with a clean version in an appendix attached hereto.

Claims

1. A method of identifying one or more defective shift register latches in a scan chain, the method comprising:

electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input;

placing the scan chain circuit into an operating region;

loading a scan test pattern into the scan chain circuit;

placing the scan chain circuit into a failing region;

applying a shift clock pulse to the clock input of the second latch, wherein the shift clock pulse is applied while the scan chain circuit is in the failing region;

placing the scan chain circuit into an operating region;

unloading the scan chain circuit; and

identifying at least one defective shift register latch in the scan chain circuit.

2. The method of claim 1, further comprising:

analyzing output from the scan chain circuit after the unloading.

3. The method of claim 1, wherein the loading a scan test pattern into the scan chain circuit includes loading a scan test pattern of all zeroes.

4. The method of claim 1, wherein the loading a scan test pattern into the scan chain circuit includes loading of all ones.

5. The method of claim 1, wherein the loading a scan test pattern into the scan chain circuit includes loading zero and ones.

6. The method of claim 5, wherein the loading a scan test pattern into the scan chain circuit includes loading an algorithmic scan test pattern.

7. The method of claim 1, wherein the unloading comprises:

applying a scan clock pulse to the clock input of the first latch and a shift clock pulse to the input of the second latch, wherein the scan pulse and the shift clock pulse are applied while the scan chain circuit is in the operating region;

measuring an output of the second latch against an expected response;

recording the output;

checking whether the scan chain circuit has been completed; and

repeating the applying the scan clock pulse and the shift clock pulse, the measuring the output of the second latch, and the recording until the scan chain circuit is completed.

8. A method of identifying one or more defective shift register latches in a scan chain, the method comprising:

electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input;

placing the scan chain circuit into an operating region;

loading a scan test pattern into the scan chain circuit;

placing the scan chain circuit into a failing region;

applying a scan clock pulse to the clock input of the first latch, wherein the scan clock pulse is applied while the scan chain circuit is in the failing region;

placing the scan chain circuit into an operating region;

applying a shift clock pulse to the clock input of the second latch, wherein the shift clock pulse is applied while the scan chain circuit is in the operating region;

unloading the scan chain circuit; and

identifying at least one defective shift register latch in the scan chain circuit.

9. The method of claim 8, further comprising:

analyzing output from the scan chain circuit after the unloading the scan chain.

10. The method of claim 8, wherein the loading a scan test pattern into the scan chain circuit includes loading a scan test pattern of all zeroes.

11. The method of claim 8, wherein the loading a scan test pattern into the scan chain circuit includes loading a scan test pattern of all ones.

12. The method of claim 8, wherein the loading a scan test pattern into the scan chain circuit includes loading zero and ones.

13. The method of claim 12, wherein the loading a scan test pattern into the scan chain circuit includes loading an algorithmic scan test pattern.

14. The method of claim 8, wherein the unloading comprises:

applying a scan clock pulse to the clock input of the first latch and a shift clock pulse to the input of the second latch, wherein the scan pulse and the shift clock pulse are applied while the scan chain circuit is in the operating region;

measuring an output of the second latch against an expected response;

recording the output;

checking whether the scan chain circuit has been completed; and

repeating the applying the scan clock pulse and the shift clock pulse, the measuring the output of the second latch, and the recording until the scan chain circuit is completed.

15. A method of identifying one or more defective shift register latches in a scan chain, the method comprising:

electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input;

placing the scan chain circuit into an operating region;

loading a scan test pattern into the scan chain circuit;

placing the scan chain circuit into a failing region;

applying a scan clock pulse to the clock input of the first latch, wherein the scan clock pulse is applied while the scan chain circuit is in the failing region;

applying a shift clock pulse to the clock input of the second latch, wherein the shift clock pulse is applied while the scan chain circuit is in the failing region;

placing the scan chain circuit into an operating region;

unloading the scan circuit; and

identifying at least one defective shift register latch in the scan chain circuit.

16. The method of claim 15, further comprising:

applying a shift clock pulse to the clock input of the second latch prior to unloading the latch.

17. The method of claim 15, wherein the loading a scan test pattern into the scan chain circuit includes loading a scan test pattern of all zeroes.

18. The method of claim 15, wherein the loading a scan test pattern into the scan chain circuit includes loading a scan test pattern of all ones.

19. The method of claim 15, wherein the loading a scan test pattern into the scan chain circuit includes loading zero and ones.

20. The method of claim 19, wherein the loading a scan test pattern into the scan chain circuit includes loading an algorithmic scan test pattern.

21. A computer program product containing programming instructions for identifying one or more defective shift register latches in a scan chain, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input, the programming instructions comprising:

placing the scan chain circuit into an operating region;

loading a scan test pattern into the scan chain circuit;

placing the scan chain circuit into a failing region;

applying a shift clock pulse to the clock input of the second latch, wherein the shift clock pulse is applied while the scan chain circuit is in the operating region

placing the scan chain circuit into an operating region;

unloading the scan circuit; and

identifying at least one defective shift register latch in the scan chain circuit.

22. A computer program product containing programming instructions for identifying one or more defective shift register latches in a scan chain, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input, the programming instructions comprising:

placing the scan chain circuit into an operating region;

loading a scan test pattern into the scan chain circuit;

placing the scan chain circuit into a failing region;

applying a scan lock pulse to the clock input of the first latch, wherein the scan clock pulse is applied while the scan chain circuit is in the operating region;

applying a shift clock pulse to the clock input of the second latch, wherein the shift clock pulse is applied while the scan chain circuit is in the operating region;

placing the scan chain circuit into an operating region;

unloading the scan circuit; and

identifying at least one defective shift register latch in the scan chain circuit.