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Diagnostic method for detection of multiple defects in a Level Sensitive Scan Design (LSSD)

  • US 7,107,502 B2
  • Filed: 01/29/2004
  • Issued: 09/12/2006
  • Est. Priority Date: 01/29/2004
  • Status: Expired due to Fees
First Claim
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1. A method of identifying one or more defective shift register latches in a scan chain, the method comprising:

  • electrically coupling a plurality of shift register latches into a series configuration so as to form a scan chain circuit, wherein each of the shift register latches includes a first latch and a second latch connected in a master-slave configuration, wherein each of the first latch and second latch includes at least one clock input;

    placing the scan chain circuit into an operating region;

    loading a scan test pattern into the scan chain circuit;

    placing the scan chain circuit into a failing region;

    applying a shift clock pulse to the clock input of the second latch, wherein the shift clock pulse is applied while the scan chain circuit is in the failing region;

    placing the scan chain circuit into an operating region;

    unloading the scan chain circuit; and

    identifying at least one defective shift register latch in the scan chain circuit.

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