Concatenated turbo product codes for high performance satellite and terrestrial communications

• US 7,107,505 B2
• Filed: 03/27/2002
• Issued: 09/12/2006
• Est. Priority Date: 03/27/2001
• Status: Expired due to Fees

• Current Assignee: Comtech EF Data (Comtech Telecommunications Corporation)
• Original Assignee: Comtech Aha Corporation (Comtech Telecommunications Corporation)
• Inventors: Thesling, William H. III
• Primary Examiner(s): Lamarre, Guy J.
• Application Number:
  US10/109,315
• Publication Number:
  US 20020162072A1
• Time in Patent Office: 1,630 Days
• Field of Search: 714/755, 714/757, 714/777, 714/786, 714/792, 714/795, 714/800, 714/701, 341/50
• US Class Current: 714/755
• CPC Class Codes: H03M 13/19 Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
• CPC Class Codes: H03M 13/2742 Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators
• CPC Class Codes: H03M 13/2945 using at least three error correction codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2963 Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
• CPC Class Codes: H03M 13/618 Shortening and extension of codes

Abstract

Architecture for enhancing the encoding/decoding of information of a channel. A stream of incoming information bits are arranged into a first array of information bits. The first array of information bits are processed into a first code of bits, which bits form a plurality of first code words having a minimum distance to neighboring error events. Selected bits of the first code are rearranged into a second array of bits by intermittent successive rotations of the selected bits of the first code. A second code is then generated from the second array of bits to increase the minimum distance to the neighboring error events.

Claims

1. A method of encoding data of a data channel, the method comprising:

arranging a stream of incoming information bits into an information bit array;

processing the information bit array to generate a row of column parity bits;

encoding rows of the information bit array and rows of the column parity bits to generate a first row parity bits and a first column/row parity bits, wherein the information bit array, the column parity bits, the first row parity bits and the first column/row parity bits define a first Turbo Product Code;

randomizing the information bit array and the column parity bits by cyclically rotating columns of information bits to generate a rotated information bit array, wherein the randomizing includes utilizing rotation indexing where each column is rotated an equal number of bit places N, and wherein a column associated with a number of a parity check bits is rotated any number of bit places except N;

encoding rows of the rotated information bit array to generate a second row parity bits and a second column/row parity bits, wherein the rotated information bit array, the second row parity bits, the second column/row parity bits and the first column parity bits define a second Turbo Product Code.

2. A method of encoding data of a data channel, the method comprising:

arranging a stream of incoming information bits into a k-by-k array of information bits;

processing the k-by-k array of information bits by appending rows of column parity bits to lower bits of the array to form a (n+1, k) Extended Hamming Code, wherein the (n+1, k) Extended Hamming Code has k columns that include the information bits and has n+1-k rows that include only the column parity bits;

encoding rows of the (n+1, k) Extended Hamming Code to generate a first row parity bits and a second column/row parity bits, wherein the (n+1, k) Extended Hamming Code, the first row parity bits and the first column/row parity bits define a first Turbo Product Code;

randomizing selected bits of the (n+1, k) Extended Hamming Code into a randomized (n+1, k) Extended Hamming Code by rotating k columns of the (n+1, k) Extended Hamming Code in a staggered diagonal rotation, wherein the randomizing includes utilizing rotation indexing where each column is rotated an equal number of bit places N, and wherein a column associated with a number of a parity check bits is rotated any number of bit places except N;

encoding the randomized (n+1, k) Extended Hamming Code to generate a second row parity bits and a second column/row parity bits; and

multiplexing the first Turbo Product Code with both the second row parity bits and the second column/row parity bits to generate a second Turbo Product Code.

3. An encoder configured to encode data of a data channel, the encoder comprising:

a sampler configured to arrange a stream of incoming information bits into a k-by-k array of information bits;

a processing block configured to process the k-by-k array of information bits by appending rows of column parity bits to lower bits of the array to form a (n+1, k) Extended Hamming Code, wherein the (n+1, k) Extended Hamming Code has k columns that include the information bits and has n+1-k rows that include only the column parity bits;

a second processing block configured to encode rows of the (n+1, k) Extended Hamming Code to generate a first row parity bits and a second column/row parity bits, wherein the (n+1, k) Extended Hamming Code, the first row parity bits and the first column/row parity bits define a first Turbo Product Code;

a rotator configured to randomize selected bits of the (n+1, k) Extended Hamming Code into a randomized (n+1, k) Extended Hamming Code by rotating k columns of the (n+1, k) Extended Hamming Code in a staggered diagonal rotation, wherein the rotator utilizes rotation indexing where each column is rotated an equal number of bit places N, and wherein a column associated with a number of a parity check bits is rotated any number of bit places except N;

a third processing block configured to encode the randomized (n+1, k) Extended Hamming Code to generate a second row parity bits and a second column/row parity bits; and

a multiplexor configured to multiplex the first Turbo Product Code with both the second row parity bits and the second column/row parity bits to generate a second Turbo Product Code.