Low density parity check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses

• US 7,107,511 B2
• Filed: 02/19/2003
• Issued: 09/12/2006
• Est. Priority Date: 08/15/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): Chase, Shelly A
• Application Number:
  US10/369,168
• Publication Number:
  US 20040034827A1
• Time in Patent Office: 1,301 Days
• Field of Search: 714/794, 714/795, 714/796, 714/791, 375/262, 375/265, 375/341
• US Class Current: 714/794
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence

Abstract

Low Density Parity Check (LDPC) code decoder using min*, min**, max* or max** and their respective inverses. For the first time, min* processing is demonstrated for use in decoding LDPC-coded signals. In addition, max*, min**, or max** (and their respective inverses) may also be employed when performing calculations that are required to perform decoding of signals coded using LDPC code. These new parameters may be employed to provide for much improved decoding processing for LDPC codes when that decoding involves the determination of a minimal and/or maximal value, or a minimal and/or maximal log corrected value, from among a number of possible values. The total number of processing steps employed within the decoding of an LDPC-coded signal is significantly reduced be employing the min*, max*, min**, or max** (and their respective inverses) decoding processing described herein.

Claims

1. A Low Density Parity Check (LDPC) code Log-Likelihood Ratio (LLR) decoder that is operable to decode a bit within a signal, the decoder comprising:

an initialization functional block that computes a Log-Likelihood ratio (LLR) of a channel metric and assigns an initial value of a variable node extrinsic information value to be the LLR of the channel metric, the channel metric corresponding to a communication channel over which the signal is communicated;

a check node processing functional block that computes a check node extrinsic information value using the value of the variable node extrinsic information value by employing min* processing, min** processing, max* processing, or max** processing;

a variable node processing functional block that computes a variable node extrinsic information value using the value of the variable node extrinsic information value and the check node extrinsic information value;

wherein the variable node processing functional block provides the variable node extrinsic information value as feedback to the check node processing functional block to perform a plurality of decoding iterations; and

a variable bit estimation functional block that estimates a value of the bit within the signal using the variable node extrinsic information value.

2. The decoder of claim 1, wherein the check node processing functional block identifies a plurality of check node edges before computing the check node extrinsic information value.

3. The decoder of claim 1, wherein the variable node processing functional block identifies a plurality of variable node edges before computing the variable node extrinsic information value.

4. The decoder of claim 1, wherein the min* processing that may be employed by the check node processing functional block comprises min*+ processing using a corresponding plurality of variable node extrinsic information values thereby generating an intermediate variable A.

5. The decoder of claim 4, wherein the check node processing functional block is operable to perform the min*+ processing in at least one of a parallel min*+ implementation, a single stage min*+ implementation, and a serial min*+ implementation.

6. The decoder of claim 4, wherein the min* processing that may be employed by the check node processing functional block comprises min*−

processing using the intermediate variable A and a corresponding variable node extrinsic information value of the plurality of variable node extrinsic information values.

7. The decoder of claim 6, wherein the check node processing functional block is operable to perform the min*−

processing in at least one of a parallel min*−

implementation that simultaneously calculates a plurality of possible min*−

values and a serial min*−

implementation that sequentially calculates the plurality of possible min*−

values.

8. The decoder of claim 1, wherein the min** processing that may be employed by the check node processing functional block comprises min**+ processing using a corresponding plurality of variable node extrinsic information values thereby generating an intermediate variable A.

9. The decoder of claim 8, wherein the check node processing functional block performs the min**+ processing in at least one of a parallel min**+ implementation, a single stage min**+ implementation, and a serial min**+ implementation.

10. The decoder of claim 8, wherein the min** processing employed by the check node processing functional block comprises min**−

processing using the intermediate variable A and a variable node extrinsic information value of the plurality of variable node extrinsic information values.

11. The decoder of claim 10, wherein the check node processing functional block is operable to perform the min**−

processing in at least one of a parallel min**−

implementation that simultaneously calculates a plurality of possible min*−

values and a serial min**−

implementation that sequentially calculates the plurality of possible min**−

values.

12. The decoder of claim 1, wherein the max* processing that may be employed by the check node processing functional block comprises max*+ processing using a corresponding plurality of variable node extrinsic information values thereby generating an intermediate variable A.

13. The decoder of claim 12, wherein the check node processing functional block performs the max*+ processing in at least one of a parallel max*+ implementation, a single stage max*+ implementation, and a serial max*+ implementation.

14. The decoder of claim 12, wherein the max* processing employed by the check node processing functional block comprises max*−

processing using the intermediate variable A and a variable node extrinsic information value of the plurality of variable node extrinsic information values.

15. The decoder of claim 14, wherein the check node processing functional block is operable to perform the max*−

processing in at least one of a parallel max*−

implementation that simultaneously calculates a plurality of possible max*−

values and a serial max*−

implementation that sequentially calculates the plurality of possible max*−

values.

16. The decoder of claim 1, wherein the max** processing that may be employed by the check node processing functional block comprises max**+ processing using a corresponding plurality of variable node extrinsic information values thereby generating an intermediate variable A.

17. The decoder of claim 16, wherein the check node processing functional block performs the max**+ processing in at least one of a parallel max**+ implementation, a single stage max**+ implementation, and a serial max**+ implementation.

18. The decoder of claim 16, wherein the max** processing employed by the check node processing functional block comprises max**−

processing using the intermediate variable A and a variable node extrinsic information value of the plurality of variable node extrinsic information values.

19. The decoder of claim 18, wherein the check node processing functional block is operable to perform the min*−

processing in at least one of a parallel max**−

implementation that simultaneously calculates a plurality of possible max**−

values and a serial max**−

implementation that sequentially calculates the plurality of possible max**−

values.

20. The decoder of claim 16, wherein the decoder is implemented within a communication receiver;

and

the communication receiver is contained within at least one of a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

21. The decoder of claim 1, wherein the signal is one of a regular LDPC code signal and an irregular LDPC code signal.

22. The decoder of claim 1, wherein the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

23. The decoder of claim 1, wherein the decoder is implemented within a communication receiver;

and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

24. A forward/backward Low Density Parity Check (LDPC) code decoder that is operable to decode a bit within a signal, the decoder comprising:

an initialization functional block that computes a logarithmic metric value of the signal;

a forward and backward check node processing functional block that employs min* processing or max* processing to calculate a plurality of forward metric values (alphas) and a plurality of backward metric values (betas) using an initial plurality of variable node extrinsic information values;

an extrinsic information value calculation functional block that employs min* processing or max* processing to calculate a plurality of check node extrinsic values using the plurality of forward metric values (alphas) and the plurality of backward metric values (betas);

wherein the extrinsic information value calculation functional block also employs min* processing or max* processing to calculate a plurality of variable node extrinsic values using the logarithmic metric value of the signal and the plurality of check node extrinsic values;

wherein the extrinsic information value calculation functional block that sums a variable node extrinsic value of the plurality of variable node extrinsic values and a check node extrinsic value of the plurality of check node extrinsic values;

wherein the extrinsic information value calculation functional block provides the sum generated by the extrinsic information value calculation functional block as feedback to the forward and backward check node processing functional block to perform a plurality of decoding iterations; and

a variable bit estimation functional block that estimates a value of the bit within the signal using the sum generated by the extrinsic information value calculation functional block.

25. The decoder of claim 24, wherein the initialization functional block computes a logarithmic metric of the signal in real time using a stored logarithmic ratio of metrics.

26. The decoder of claim 24, wherein the initialization functional block employs a stored logarithmic ratio of metrics or components of the logarithmic ratio of metrics.

27. The decoder of claim 24, wherein the min* processing is performed in at least one of a parallel min* implementation, a single stage min* implementation, and a serial min* implementation.

28. The decoder of claim 24, wherein the max* processing is performed in at least one of a parallel max* implementation, a single stage max* implementation, and a serial max* implementation.

29. The decoder of claim 24, wherein the signal is one of a regular LDPC code signal and an irregular LDPC code signal.

30. The decoder of claim 24, wherein the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

31. The decoder of claim 24, wherein the decoder is implemented within a communication receiver;

and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

32. A Low Density Parity Check (LDPC) code Log-Likelihood Ratio (LLR) decoding method that decodes an LDPC coded signal, the method comprising:

computing a LLR of a channel metric;

during a first decoding iteration, setting a variable node extrinsic information to be the LLR of the channel metric;

identifying a set of check node edges;

computing a check node extrinsic information value using the variable node extrinsic information value by employing min* processing, min** processing, max* processing, or max** processing;

identifying a set of variable node edges;

computing a variable node extrinsic information value using the LLR of the channel metric and the check node extrinsic information value;

feeding back the variable node extrinsic information value for use in computing a subsequent check node extrinsic information value when performing iterative decoding; and

estimating a variable bit value using the variable node extrinsic information value.

33. The method of claim 32, wherein the min* processing comprises min*+ processing using a plurality of variable node extrinsic information values thereby generating an intermediate variable A.

34. The method of claim 33, wherein the min*+ processing is performed in at least one of a parallel min*+ implementation, a single stage min*+ implementation, and a serial min*+ implementation.

35. The method of claim 33, wherein the min* processing comprises min*−

processing using the intermediate variable A and a variable node extrinsic information value of the plurality of variable node extrinsic information values.

36. The method of claim 35, the min*−

processing is performed in at least one of a parallel min*−

implementation that simultaneously calculates a plurality of possible min*−

values and a serial min*−

implementation that sequentially calculates the plurality of possible min*−

values.

37. The method of claim 32, wherein the min** processing comprises min**+ processing using a plurality of variable node extrinsic information values thereby generating an intermediate variable A.

38. The method of claim 37, wherein the min**+ processing is performed in at least one of a parallel min**+ implementation, a single stage min**+ implementation, and a serial min**+ implementation.

39. The method of claim 37, wherein the min** processing comprises min**−

processing using the intermediate variable A and a variable node extrinsic information value of the plurality of variable node extrinsic information values.

40. The method of claim 39, the min**−

processing is performed in at least one of a parallel min**−

implementation that simultaneously calculates a plurality of possible min**−

values and a serial min**−

implementation that sequentially calculates the plurality of possible min**−

values.

41. The method of claim 32, wherein the max* processing comprises max*+ processing using a plurality of variable node extrinsic information values thereby generating an intermediate variable A.

42. The method of claim 41, wherein the max*+ processing is performed in at least one of a parallel max*+ implementation, a single stage max*+ implementation, and a serial max*+ implementation.

43. The method of claim 41, wherein the max* processing comprises max*−

processing using the intermediate variable A and a variable node extrinsic information value of the plurality of variable node extrinsic information values.

44. The decoder of claim 43, the max*−

processing is performed in at least one of a parallel max*−

implementation that simultaneously calculates a plurality of possible max*−

values and a serial min*−

implementation that sequentially calculates the plurality of possible max*−

values.

45. The method of claim 32, wherein the max** processing comprises max**+ processing using a plurality of variable node extrinsic information values thereby generating an intermediate variable A.

46. The method of claim 45, wherein the max**+ processing is performed in at least one of a parallel max**+ implementation, a single stage max**+ implementation, and a serial max**+ implementation.

47. The method of claim 45, wherein the max** processing comprises max**−

processing using the intermediate variable A and a variable node extrinsic information value of the plurality of variable node extrinsic information values.

48. The method of claim 47, the max**−

processing is performed in at least one of a parallel max**−

implementation that simultaneously calculates a plurality of possible max**−

values and a serial max**−

implementation that sequentially calculates the plurality of possible max**−

values.

49. The method of claim 32, wherein the LDPC coded signal is one of a regular LDPC code signal and an irregular LDPC code signal.

50. The method of claim 32, wherein the method is performed within a decoder;

and

the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

51. The method of claim 32, wherein the method is performed within a decoder;

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

52. A Low Density Parity Check (LDPC) code forward/backward decoding method, the method comprising:

retrieving a ratio of logarithmic metrics;

calculating a logarithmic metric value of a signal using the ratio of logarithmic metrics;

generating a plurality of initial values for a plurality of forward metric values (alphas) and a plurality of backward metric values (betas);

calculating a plurality of values for the plurality of forward metric values (alphas) by performing min* processing of an initial plurality of variable node extrinsic information values;

calculating a plurality of values for the plurality of backward metric values (betas) by performing min* processing or max* processing of an initial plurality of variable node extrinsic information values;

calculating a plurality of check node extrinsic information values by performing min* processing on the plurality of forward metric values (alphas) and the plurality of backward metric values (betas);

calculating a plurality of variable node extrinsic information values by performing min* processing or max* processing on the logarithmic metric value of the signal and the plurality of check node extrinsic values;

summing the plurality of check node extrinsic information values and the plurality of variable node extrinsic information values thereby generating a sum;

feeding back the sum of the plurality of check node extrinsic information values and the plurality of variable node extrinsic information values for use in calculating a subsequent plurality of values for the plurality of forward metric values (alphas) when performing iterative decoding; and

estimating a variable bit value using the sum.

53. The method of claim 52, wherein the min* processing is performed in at least one of a parallel min* implementation, a single stage min* implementation, and a serial min* implementation.

54. The method of claim 52, wherein the max* processing is performed in at least one of a parallel max* implementation, a single stage max* implementation, and a serial max* implementation.

55. The method of claim 52, wherein the LDPC coded signal is one of a regular LDPC code signal and an irregular LDPC code signal.

56. The method of claim 52, wherein the method is performed within a decoder;

and

the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

57. The method of claim 52, wherein the method is performed within a decoder;

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

58. A decoder that is operable to perform min** processing by employing min**−

and min**+ processing, comprising;

a min**+ functional block that performs min**+ processing on a plurality of min** inputs thereby generating an intermediate variable; and

a min**−

functional block that performs min**−

processing on each of the min** inputs of the plurality of min** inputs and the intermediate variable thereby generating a plurality of min** outputs.

59. The decoder of claim 58, wherein the min**+ processing operates on two elements, the two elements comprising two min** inputs of the plurality of min** inputs.

60. The decoder of claim 58, wherein the min**−

processing operates on two elements, the two elements comprising one min** input of the plurality of min** inputs and the intermediate variable.

61. The decoder of claim 58, wherein the min**+ functional block performs a number of min**+ processes, the number of min**+ processes being less than a number of min** inputs of the plurality of min** inputs.

62. The decoder of claim 58, wherein the min**−

functional block performs a number of min**−

processes, the number of min**−

processes being equal to a number of min** inputs of the plurality of min** inputs.

63. The decoder of claim 58, wherein the min**+ processing comprises an inverse function of the min**−

processing on the plurality of min** inputs.

64. The decoder of claim 58, wherein the decoder is operable to perform straightforward min** processing on the plurality of min** inputs.

65. The decoder of claim 58, wherein the decoder is operable to perform intermediate result sharing min** processing.

66. The decoder of claim 58, wherein the decoder is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, and an advanced modulation satellite receiver.

67. The decoder of claim 58, wherein the decoder is implemented within a communication receiver;

and

the communication receiver is contained within at least one of a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

68. A decoder that is operable to perform min** processing by employing min**−

and min**+ processing, comprising;

a min**+ functional block that sequentially performs min**+ processing on two min** input elements, the two min** input elements selected from a plurality of min** inputs, thereby generating an intermediate variable; and

a min**−

functional block that sequentially performs min**−

processing on two elements, the two elements comprising one of the min** inputs of the plurality of min** inputs and the intermediate variable, thereby generating a plurality of min** outputs; and

wherein the min**+ functional block performs a number of min**+ processes, the number of min**+ processes being less than a number of min** inputs of the plurality of min** inputs;

the min**−

functional block performs a number of min**−

processes, the number of min**−

processes being equal to the number of min** inputs of the plurality of min** inputs; and

the min**+ processing comprises an inverse function of the min**−

processing.

69. The decoder of claim 68, wherein the decoder is operable to perform straightforward min** processing on the plurality of min** inputs.

70. The decoder of claim 68, wherein the decoder is operable to perform intermediate result sharing min** processing on the plurality of min** inputs.

71. The decoder of claim 68, wherein the decoder is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, and an advanced modulation satellite receiver.

72. The decoder of claim 68, wherein the decoder is implemented within a communication receiver;

and

the communication receiver is contained within at least one of a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

73. A decoder that is operable to perform max** processing by employing max**−

and max**+ processing, comprising;

a max**+ functional block that performs max**+ processing on a plurality of max** inputs thereby generating an intermediate variable; and

a max**−

functional block that performs max**−

processing on each of the max** inputs of the plurality of max** inputs and the intermediate variable thereby generating a plurality of max** outputs.

74. The decoder of claim 73, wherein the max**+ processing operates on two elements, the two elements comprising two max** inputs of the plurality of max** inputs.

75. The decoder of claim 73, wherein the max**−

processing operates on two elements, the two elements comprising one max** input of the plurality of max** inputs and the intermediate variable.

76. The decoder of claim 73, wherein the max**+ functional block performs a number of max**+ processes, the number of max**+ processes being less than a number of max** inputs of the plurality of max** inputs.

77. The decoder of claim 73, wherein the max**−

functional block performs a number of max**−

processes, the number of max**−

processes being equal to a number of max** inputs of the plurality of max** inputs.

78. The decoder of claim 73, wherein the max**+ processing comprises an inverse function of the max**−

processing.

79. The decoder of claim 73, wherein the decoder is operable to perform straightforward max** processing on the plurality of max** inputs.

80. The decoder of claim 73, wherein the decoder is operable to perform intermediate result sharing max** processing on the plurality of max** inputs.

81. The decoder of claim 73, wherein the decoder is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, and an advanced modulation satellite receiver.

82. A decoder that is operable to perform max** processing by employing max**−

and max**+ processing, comprising;

a max**+ functional block that sequentially performs max**+ processing on two max** input elements, the two max** input elements selected from a plurality of max** inputs, thereby generating an intermediate variable; and

a max**−

functional block that sequentially performs max**−

processing on two elements, the two elements comprising one of the max** inputs of the plurality of max** inputs and the intermediate variable, thereby generating a plurality of max** outputs; and

wherein the max**+ functional block performs a number of max**+ processes, the number of max**+ processes being less than a number of max** inputs of the plurality of max** inputs;

the max**−

functional block performs a number of max**−

processes, the number of max**−

processes being equal to the number of max** inputs of the plurality of max** inputs; and

the max**+ processing comprises an inverse function of the max**−

processing.

83. The decoder of claim 82, wherein the decoder is operable to perform straightforward max** processing.

84. The decoder of claim 82, wherein the decoder is operable to perform intermediate result sharing max** processing.

85. The decoder of claim 82, wherein the decoder is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, and an advanced modulation satellite receiver.

86. The decoder of claim 82, wherein the decoder is implemented within a communication receiver;

and

the communication receiver is contained within at least one of a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

87. A min** processing method that employs min**−

and min**+ processing, the method comprising;

performing min**+ processing on a plurality of min** inputs thereby generating an intermediate variable; and

performing min**−

processing on each of the min** inputs of the plurality of min** inputs and the intermediate variable thereby generating a plurality of min** outputs.

88. The method of claim 87, wherein the min**+ processing operates on two elements, the two elements comprising two min** inputs of the plurality of min** inputs.

89. The method of claim 87, wherein the min**−

processing operates on two elements, the two elements comprising one min** input of the plurality of min** inputs and the intermediate variable.

90. The method of claim 87, wherein the min**+ processing performs a number of min**+ processes, the number of min**+ processes being less than a number of min** inputs of the plurality of min** inputs.

91. The method of claim 87, wherein the min**−

processing performs a number of min**−

processes, the number of min**−

processes being equal to a number of min** inputs of the plurality of min** inputs.

92. The method of claim 87, wherein the min**+ processing comprises an inverse function of the min**−

processing.

93. The method of claim 87, further comprising performing straightforward min** processing on the plurality of min** inputs.

94. The method of claim 87, further comprising performing intermediate result sharing min** processing on the plurality of min** inputs.

95. The method of claim 87, wherein the method is performed within a decoder;

and

the decoder is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, and an advanced modulation satellite receiver.

96. The method of claim 87, wherein the method is performed within a decoder;

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

97. A max** processing method that employs max**−

and max**+ processing, the method comprising;

performing max**+ processing on a plurality of max** inputs thereby generating an intermediate variable; and

performing max**−

processing on each of the max** inputs of the plurality of max** inputs and the intermediate variable thereby generating a plurality of max** outputs.

98. The method of claim 97, wherein the max**+ processing operates on two elements, the two elements comprising two max** inputs of the plurality of max** inputs.

99. The method of claim 97, wherein the max**−

processing operates on two elements, the two elements comprising one max** input of the plurality of max** inputs and the intermediate variable.

100. The method of claim 97, wherein the max**+ processing performs a number of max**+ processes, the number of max**+ processes being less than a number of max** inputs of the plurality of max** inputs.

101. The method of claim 97, wherein the max**−

processing performs a number of max**−

processes, the number of max**−

processes being equal to a number of max** inputs of the plurality of max** inputs.

102. The method of claim 97, wherein the max**+ processing comprises an inverse function of the max**−

processing.

103. The method of claim 97, further comprising performing straightforward max** processing on the plurality of max** inputs.

104. The method of claim 97, further comprising performing intermediate result sharing max** processing on the plurality of max** inputs.

105. The method of claim 97, wherein the method is performed within a decoder;

and

the decoder is contained within at least one of a satellite receiver, a high definition television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, and an advanced modulation satellite receiver.

106. The method of claim 97, wherein the method is performed within a decoder;

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a high definition television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

107. A decoder that performs min* check node processing when decoding an LDPC (Low Density Parity Check) coded signal, the decoder comprising:

a check node processing functional block that updates a check node extrinsic information value by employing min* processing;

a min* functional block, whose operation is directed by the check node processing functional block, that performs the min* processing on a first value and a second value;

wherein the min* functional block determines a first sign function value using the first value;

wherein the min* functional block determines a second sign function value using the second value;

wherein the min* functional block determines a minimum value from among the first value and the second value;

wherein the min* functional block retrieves from a ROM (Read Only Memory) a predetermined logarithmic correction factor that is an absolute value of a difference between the first value and the second value;

wherein the min* functional block subtracts the predetermined logarithmic correction factor from the minimum value thereby generating a min* resultant; and

wherein the min* functional block multiplies the first sign function value by the second sign function value and by the min* resultant.

108. The decoder of claim 107, wherein:

the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

109. The decoder of claim 107, wherein:

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

110. A decoder that performs min* check node processing when decoding an LDPC (Low Density Parity Check) coded signal, the decoder comprising:

a check node processing functional block that updates a check node extrinsic information value by employing min* processing;

a min* functional block, whose operation is directed by the check node processing functional block, that performs the min* processing on a first value and a second value;

wherein the min* functional block determines a first sign function value using the first value;

wherein the min* functional block determines a second sign function value using the second value;

wherein the min* functional block determines a minimum value from among the first value and the second value;

wherein the min* functional block retrieves from memory a predetermined logarithmic correction factor that corresponds to the first value and the second value; and

wherein the min* functional block calculates the updated check node extrinsic information value using the first sign function value, the second sign function value, the minimum value, and the predetermined logarithmic correction factor that is retrieved from memory.

111. The decoder of claim 110, wherein:

the predetermined logarithmic correction factor is an absolute value of a difference between the first value and the second value.

112. The decoder of claim 110, wherein:

the memory from which the predetermined logarithmic correction factor is retrieved is ROM (Read Only Memory).

113. The decoder of claim 110, wherein:

the min* functional block multiplies the first sign function value by the second sign function value.

114. The decoder of claim 110, wherein:

the min* functional block subtracts the predetermined logarithmic correction factor from the minimum value.

115. The decoder of claim 110, wherein:

the min* functional block subtracts the predetermined logarithmic correction factor from the minimum value thereby generating a min* resultant; and

the min* functional block multiplies the first sign function value by the second sign function value and by the min* resultant.

116. The decoder of claim 110, wherein:

the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

117. The decoder of claim 110, wherein:

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

118. A decoder that performs min* check node processing when decoding an LDPC (Low Density Parity Check) coded signal, the decoder comprising:

a check node processing functional block that updates a check node extrinsic information value by employing min* processing;

a min* functional block, whose operation is directed by the check node processing functional block, that performs the min* processing on a first value and a second value;

wherein the min* functional block determines a first sign function value using the first value;

wherein the min* functional block determines a second sign function value using the second value;

wherein the min* functional block determines a min* resultant using the first value and the second value; and

wherein the min* functional block calculates the updated check node extrinsic information value using the first sign function value, the second sign function value, and the min* resultant.

119. The decoder of claim 118, wherein:

the min* functional block determines a minimum value from among the first value and the second value;

the min* functional block retrieves from memory a predetermined logarithmic correction factor that corresponds to the first value and the second value; and

the min* functional block subtracts the predetermined logarithmic correction factor from the minimum value thereby generating the min* resultant.

120. The decoder of claim 119, wherein:

the predetermined logarithmic correction factor is an absolute value of a difference between the first value and the second value.

121. The decoder of claim 119, wherein:

the memory from which the predetermined logarithmic correction factor is retrieved is ROM (Read Only Memory).

122. The decoder of claim 118, wherein:

the min* functional block multiplies the first sign function value by the second sign function value and by the min* resultant.

123. The decoder of claim 118, wherein:

the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

124. The decoder of claim 118, wherein:

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

125. A Low Density Parity Check (LDPC) code Log-Likelihood Ratio (LLR) decoder that is operable to decode a bit within a signal, the decoder comprising:

an initialization functional block that computes a Log-Likelihood ratio (LLR) of a channel metric and assigns an initial value of a variable node extrinsic information value to be the LLR of the channel metric, the channel metric corresponding to a communication channel over which the signal is communicated;

a check node processing functional block that computes a check node extrinsic information value using the value of the variable node extrinsic information value by employing min* processing;

a variable node processing functional block that computes a variable node extrinsic information value using the value of the variable node extrinsic information value and the check node extrinsic information value;

wherein the variable node processing functional block provides the variable node extrinsic information value as feedback to the check node processing functional block to perform a plurality of decoding iterations;

a variable bit estimation functional block that estimates a value of the bit within the signal using the variable node extrinsic information value;

wherein the check node processing functional block is operable to update the check node extrinsic information value by directing a min* functional block to perform min* processing on a first value and a second value;

wherein the min* functional block determines a first sign function value using the first value;

wherein the min* functional block determines a second sign function value using the second value;

wherein the min* functional block determines a minimum value from among the first value and the second value;

wherein the min* functional block retrieves from a ROM (Read Only Memory) a predetermined logarithmic correction factor that is an absolute value of a difference between the first value and the second value;

wherein the min* functional block subtracts the predetermined logarithmic correction factor from the minimum value thereby generating a min* resultant; and

wherein the min* functional block multiplies the first sign function value by the second sign function value and by the min* resultant.

126. The decoder of claim 125, wherein:

the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

127. The decoder of claim 125, wherein:

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

128. A method for updating a check node extrinsic information value by performing min* check node processing, the method comprising:

receiving a first value and a second value;

determining a first sign function value using the first value;

determining a second sign function value using the second value;

determining a minimum value from among the first value and the second value;

retrieving from a ROM (Read Only Memory) a predetermined logarithmic correction factor that is an absolute value of a difference between the first value and the second value;

subtracting the predetermined logarithmic correction factor from the minimum value thereby generating a min* resultant; and

multiplying the first sign function value by the second sign function value and by the min* resultant.

129. The method of claim 128, wherein:

the method is performed within a decoder; and

the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

130. The method of claim 128, wherein:

the method is performed within a decoder;

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.

131. A method for updating a check node extrinsic information value by performing min* check node processing, the method comprising:

receiving a first value and a second value;

determining a first sign function value using the first value;

determining a second sign function value using the second value;

determining a minimum value from among the first value and the second value;

retrieving from memory a predetermined logarithmic correction factor that corresponds to the first value and the second value; and

calculating the updated check node extrinsic information value using the first sign function value, the second sign function value, the minimum value, and the predetermined logarithmic correction factor that is retrieved from memory.

132. The method of claim 131, wherein:

the predetermined logarithmic correction factor is an absolute value of a difference between the first value and the second value.

133. The method of claim 131, wherein:

the memory from which the predetermined logarithmic correction factor is retrieved is ROM (Read Only Memory).

134. The method of claim 131, further comprising:

multiplying the first sign function value by the second sign function value.

135. The method of claim 131, further comprising:

subtracting the predetermined logarithmic correction factor from the minimum value.

136. The method of claim 131, further comprising:

subtracting the predetermined logarithmic correction factor from the minimum value thereby generating a min* resultant; and

multiplying the first sign function value by the second sign function value and by the min* resultant.

137. The method of claim 131, wherein:

the method is performed within a decoder; and

the decoder is contained within at least one of a satellite receiver, a High Definition Television (HDTV) set top box receiver, a base station receiver, a mobile receiver, a receiver, a mobile unit, a transceiver, an advanced modulation satellite receiver, and a Dense Wavelength Division Multiplexing (DWDM) line card.

138. The method of claim 131, wherein:

the method is performed within a decoder;

the decoder is implemented within a communication receiver; and

the communication receiver is contained within at least one of a satellite communication system, a High Definition Television (HDTV) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, and a fiber-optic communication system.