Method of integrating optical devices and electronic devices on an integrated circuit

• US 7,109,051 B2
• Filed: 11/15/2004
• Issued: 09/19/2006
• Est. Priority Date: 11/15/2004
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zia, Omar, Cave, Nigel G.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US10/989,940
• Publication Number:
  US 20060105479A1
• Time in Patent Office: 673 Days
• Field of Search: None
• US Class Current: 438/29
• CPC Class Codes: H01L 27/144 Devices controlled by radiation
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission

Abstract

A method for integrating an optical device and an electronic device on a semiconductor substrate comprises forming openings within an active semiconductor layer in a first region of the semiconductor substrate, wherein the first region corresponds to an electronic device portion and the second region corresponds to an optical device portion. A semiconductor layer is epitaxially grown overlying an exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region. At least a portion of an electronic device is formed on the active semiconductor layer within the electronic device portion of the semiconductor substrate. The method further includes forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device.

Claims

1. A method for integrating an optical device and an electronic device on a semiconductor substrate, comprising:

providing a semiconductor substrate having an active semiconductor layer;

forming openings within the active semiconductor layer in a first region of the semiconductor substrate and protecting the active semiconductor layer in a second region of the semiconductor substrate during the formation of openings within the active semiconductor layer in the first region, wherein the first region corresponds to an electronic device portion of the semiconductor substrate and the second region corresponds to an optical device portion of the semiconductor substrate;

filling the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate with a fill material;

exposing a portion of the active semiconductor layer in the second region of the semiconductor substrate and protecting the first region of the semiconductor substrate during the exposing of the active semiconductor layer in the second region;

epitaxially growing a semiconductor layer overlying the exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region;

forming at least a portion of an electronic device on the active semiconductor layer within the electronic device portion of the semiconductor substrate;

forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device; and

forming a further portion of the electronic device within the electronic device portion of the semiconductor substrate.

2. The method of claim 1, wherein the active semiconductor layer and the epitaxially grown semiconductor layer have a combined total thickness sufficient to create a waveguide.

3. The method of claim 1, wherein the active semiconductor layer and the epitaxially grown semiconductor layer have a combined total thickness on the order of approximately 3,000 angstroms.

4. The method of claim 1, wherein forming the portion of the electronic device includes forming a gate dielectric and a gate electrode on the active semiconductor layer within the electronic device portion of the semiconductor substrate.

5. The method of claim 4, further wherein the gate dielectric protects the optical device region in the optical device portion of the semiconductor substrate during patterning of the gate electrode in the electronic device portion of the semiconductor substrate.

6. The method of claim 4, wherein forming the portion of the electronic device further includes forming extension implant regions within the active semiconductor layer proximate the gate electrode in the electronic device portion of the semiconductor substrate.

7. The method of claim 4, wherein forming the portion of the electronic device further includes forming a spacer liner and sidewall spacers, the spacer liner being formed on exposed portions of the active semiconductor layer and the gate electrode in the electronic device portion of the semiconductor substrate and the sidewall spacers being formed on sidewalls of the gate electrode with the spacer liner in-between the gate electrode and the sidewall spacers.

8. The method of claim 7, further wherein the spacer liner protects the optical device region in the optical device portion of the semiconductor substrate during forming of the sidewall spacers in the electronic device portion of the semiconductor substrate.

9. The method of claim 1, wherein forming the portion of the electronic device includes depositing a first dielectric layer and a second dielectric layer overlying the first and second regions of the semiconductor substrate, and patterning and etching the second dielectric layer to form sidewall spacers on sidewalls of the gate electrode with a portion of the first dielectric layer in-between the gate electrode and the sidewall spacers, further wherein the first dielectric layer protects the optical device region in the optical device portion of the semiconductor substrate during patterning and etching of the sidewall spacers in the electronic device portion of the semiconductor substrate.

10. The method of claim 1, wherein forming the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate comprises etching the openings, and wherein forming the trench liner comprises an oxidation process optimized to passivate the etched sidewalls, round corners of the openings, and to optimize a stress in the active semiconductor layer between the openings of the active semiconductor layer in the electronics device portion of the semiconductor substrate.

11. The method of claim 1, further comprising forming a trench liner on sidewalls within the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate, wherein forming the trench liner comprises an oxidation process optimized to control stresses in the active semiconductor layer between the openings.

12. The method of claim 11, wherein the trench liner comprises a thickness configured to provide an optimized high performance electronic device characteristic.

13. The method of claim 1, wherein forming the openings within the epitaxially grown semiconductor layer defines an optical waveguide within the optical device region of the optical device portion of the semiconductor substrate.

14. The method of claim 1, wherein forming the further portion of the electronic device includes forming source/drain implant regions.

15. The method of claim 14, further wherein forming the source/drain implant regions also includes forming electrical contacted regions within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate.

16. The method of claim 15, further comprising:

forming a salicide blocking layer overlying the optical device portion of the semiconductor substrate;

saliciding the electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the epitaxially grown semiconductor within the optical device porion of the semiconductor substrate; and

forming an interlevel dielectric layer overlying the electronic device portion and the optical device portion of the semiconductor substrate,

wherein saliciding includes saliciding the electrical contacted regions within the epitaxially grown semiconductor layer.

17. The method of claim 16, wherein forming the salicide blocking layer comprises depositing TEOS on the optical device portion and the electronic device portion of the semiconductor substrate and then removing the TEOS from the electronic device portion.

18. The method of claim 16, wherein forming the salicide blocking layer comprises patterning the blocking layer to overlie the optical device portion of the semiconductor substrate alone.

19. The method of claim 16, wherein saliciding includes forming a salicidation metallization overlying the optical device portion and the electronic device portion of the semiconductor substrate, annealing the salicidation metallization to form salicided regions on exposed regions of semiconductor material within the electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the salicidation metallization overlying the active semiconductor layer within the optical device portion of the semiconductor substrate.

20. The method of claim 1, wherein the fill material includes one or more of TEOS, a furnace oxide, or a high density plasma oxide.

21. The method of claim 1, wherein the optical device portion of the semiconductor substrate can comprise one or more of an optical grating coupler, a waveguide, a wavelength selective filter, an optical modulator, or an arrayed waveguide grating.

22. A method for integrating an optical device and an electronic device on a semiconductor substrate, comprising:

providing a semiconductor substrate having an active semiconductor layer;

forming openings within the active semiconductor layer in a first region of the semiconductor substrate and protecting the active semiconductor layer in a second region of the semiconductor substrate during the formation of openings within the active semiconductor layer in the first region, wherein the first region corresponds to an electronic device portion of the semiconductor substrate and the second region corresponds to an optical device portion of the semiconductor substrate;

filling the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate with a fill material;

forming at least a portion of an electronic device on the active semiconductor layer within the electronic device portion of the semiconductor substrate;

depositing a first dielectric layer and a second dielectric layer overlying the first and second regions of the semiconductor substrate;

exposing a portion of the active semiconductor layer in the second region of the semiconductor substrate and protecting the first region of the semiconductor substrate during the exposing of the active semiconductor layer in the second region;

epitaxially growing a semiconductor layer overlying the exposed active semiconductor layer in the second region, the epitaxially grown semiconductor layer corresponding to an optical device region;

patterning and etching the second dielectric layer to form sidewall spacers on sidewalls of the gate electrode with a portion of the first dielectric layer in-between the gate electrode and the sidewall spacers;

forming openings within the epitaxially grown semiconductor layer of the optical device portion of the semiconductor substrate, wherein the openings define one or more features of an optical device; and

forming a further portion of the electronic device within the electronic device portion of the semiconductor substrate.

23. The method of claim 22, wherein forming the portion of the electronic device includes forming a gate dielectric and a gate electrode on the active semiconductor layer within the electronic device portion of the semiconductor substrate.

24. The method of claim 23, further wherein the gate dielectric protects the optical device region in the optical device portion of the semiconductor substrate during patterning of the gate electrode in the electronic device portion of the semiconductor substrate.

25. The method of claim 23, wherein forming the portion of the electronic device further includes forming extension implant regions within the active semiconductor layer proximate the gate electrode in the electronic device portion of the semiconductor substrate.

26. The method of claim 22, wherein the active semiconductor layer and the epitaxially grown semiconductor layer have a combined total thickness sufficient to create a waveguide.

27. The method of claim 22, wherein the active semiconductor layer and the epitaxially grown semiconductor layer have a combined total thickness on the order of approximately 3,000 angstroms.

28. The method of claim 22, wherein patterning and etching the second dielectric layer includes protecting the second region of the semiconductor substrate.

29. The method of claim 22, wherein forming the openings defines an optical waveguide within the optical device region of the optical device portion of the semiconductor substrate.

30. The method of claim 22, wherein forming the further portion of the electronic device includes forming source/drain implant regions.

31. The method of claim 30, further wherein forming the source/drain implant regions also includes forming electrical contacted regions within the epitaxially grown semiconductor layer proximate the optical waveguide within the optical device region of the optical device portion of the semiconductor substrate.

32. The method of claim 31, further comprising:

forming a salicide blocking layer overlying the optical device portion of the semiconductor substrate;

saliciding the electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the epitaxially grown semiconductor within the optical device porion of the semiconductor substrate; and

forming an interlevel dielectric layer overlying the electronic device portion and the optical device portion of the semiconductor substrate,

wherein saliciding further includes saliciding the electrical contacted regions within the epitaxially grown semiconductor layer.

33. The method of claim 32, wherein forming the salicide blocking layer comprises depositing TEOS on the optical device portion and the electronic device portion of the semiconductor substrate and then removing the TEOS from the electronic device portion.

34. The method of claim 32, wherein forming the salicide blocking layer comprises patterning the blocking layer to overlie the optical device portion of the semiconductor substrate alone.

35. The method of claim 32, wherein saliciding includes forming a salicidation metallization overlying the optical device portion and the electronic device portion of the semiconductor substrate, annealing the salicidation metallization to form salicided regions on exposed regions of semiconductor material within the electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the salicidation metallization overlying the active semiconductor layer within the optical device portion of the semiconductor substrate.

36. The method of claim 22, wherein the fill material includes one or more of TEOS, a furnace oxide, or a high density plasma oxide.

37. The method of claim 22, wherein the optical device portion of the semiconductor substrate can comprise one or more of an optical grating coupler, a waveguide, a wavelength selective filter, an optical modulator, or an arrayed waveguide grating.