Semiconductor integrated device including support substrate fastened using resin, and manufacturing method thereof

• US 7,109,062 B2
• Filed: 02/05/2004
• Issued: 09/19/2006
• Est. Priority Date: 02/06/2003
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okigawa, Mitsuru
• Primary Examiner(s): THAI, LUAN C
• Application Number:
  US10/773,088
• Publication Number:
  US 20050009238A1
• Time in Patent Office: 957 Days
• Field of Search: 257431-435, 257789-790, 438/48, 438/69, 438/127
• US Class Current: 438/118
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/83136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49894 Materials of the insulating layers or coatings
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 27/14683 : Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/148 : Charge coupled imagers individual charge coupled devices H01L29/765
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01016 : Sulfur [S]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor integrated device, provided with a semiconductor chip on which a semiconductor integrated circuit is formed and a support substrate laminated on at least one surface of the semiconductor chip, wherein the semiconductor chip and the support substrate are fastened using resin having particle-the minimum film thickness of the resin is larger than the maximum particle diameter of the filler.

Claims

1. A method of manufacturing a semiconductor integrated device, comprising:

a first step of laminating a semiconductor substrate on which a plurality of semiconductor chips are formed and a support substrate with resin mixed with microparticles being interposed between the semiconductor substrate and the support substrate;

a second step of pushing the support substrate against the semiconductor substrate;

a third step of arranging wiring to achieve contact from the semiconductor chips; and

a fourth step of dividing the semiconductor chips alone scrub lines to form the semiconductor integrated device, and wherein

in the second step, the support substrate is pushed against the semiconductor substrate while keeping a distance between the semiconductor substrate and the support substrate larger than the maximum particle diameter of the microparticles.

2. The method of manufacturing a semiconductor device of claim 1, further comprising a step of hardening the resin by subjecting it to a heat treatment process after the second step, and wherein in the second step the distance between the semiconductor substrate and the support substrate is kept larger than the sum of a contraction amount by which the film thickness of the resin contracts during the hardening step and the maximum particle diameter of the microparticles.

3. The method of manufacturing a semiconductor device of claim 1, further comprising, before the first step, a step of etching the semiconductor substrate to reduce the thickness of the semiconductor substrate.

4. A method of manufacturing a semiconductor integrated device, comprising:

a first step of coating a first resin layer mixed with microparticles on at least one surface of a semiconductor substrate on which a semiconductor integrated circuit is formed;

a second step of hardening the first resin layer coated in the first step; and

a third step of coating a second resin layer not containing microparticles on the first resin layer hardened in the second step, wherein

in the second step, hardening is carried out so that the film thickness of the first resin layer after hardening is kept larger than the maximum particle diameter of the microparticles.

5. The method of manufacturing a semiconductor device of claim 4, further comprising, before the first step, a step of etching a rear surface of the semiconductor substrate to make the semiconductor substrate thin.