Method for manufacturing semiconductor device having metal silicide

• US 7,109,108 B2
• Filed: 09/13/2004
• Issued: 09/19/2006
• Est. Priority Date: 10/09/1992
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Teramoto, Satoshi, Takemura, Yasuhiko, Zhang, Hongyong
• Primary Examiner(s): Coleman, W. David
• Assistant Examiner(s): Tobergte, Nicholas J
• Application Number:
  US10/938,500
• Publication Number:
  US 20050037549A1
• Time in Patent Office: 736 Days
• Field of Search: 438/630, 438/623, 438/142, 438/149
• US Class Current: 438/630
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal, and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 μm or less in width, and allowing the metal to react with silicon.

A high performance TFT can be realized. The metal silicide layer achieves favorable contact with the source and the drain, and, since it has a lower resistivity than silicon, the parasitic resistance between the source and drain regions can be considerably lowered.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of:

forming a semiconductor film over a substrate;

crystallizing the semiconductor film by irradiating a laser light;

forming a silicon oxide film in contact with the crystalline semiconductor film by using organic silane;

forming a gate electrode in contact with the gate insulating film;

forming a metal layer in contact with a portion of the crystalline semiconductor film; and

forming a metal silicide layer by reacting the metal layer with the portion of the crystalline semiconductor film by irradiating a laser light.

2. A method according to claim 1, wherein the method further comprises a step of removing a portion of the metal layer which did not react with the portion of the crystalline semiconductor film.

3. A method according to claim 1, wherein the organic silane is TEOS.

4. A method according to claim 1, wherein the metal silicide layer comprises a material selected from the group consisting of TiSi, TiSi₂, MoSi₂, WSi₂, W(SiAl)₂, Ti₇Si₁₂Al₅ and Pd₄SiAl₃.

13. A method according to claim 1, wherein the metal layer comprises a material selected from the group consisting of Mo, W, Pt, Cr, Ti and Co.

5. A method for manufacturing a semiconductor device comprising the steps of:

forming a semiconductor film over a substrate;

crystallizing the semiconductor film by irradiating a laser light;

forming a silicon oxide film in contact with the crystalline semiconductor film by using organic silane;

forming a gate electrode in contact with the gate insulating film;

forming a metal layer in contact with a portion of the crystalline semiconductor film; and

forming a metal suicide layer by reacting the metal layer with the portion of the crystalline semiconductor film by irradiating an infrared light.

6. A method according to claim 5, wherein the method further comprises a step of removing a portion of the metal layer which did not react with the portion of the crystalline semiconductor film.

7. A method according to claim 5, wherein the organic silane is TEOS.

8. A method according to claim 5, wherein the metal silicide layer comprises a material selected from the group consisting of TiSi, TiSi₂, MoSi₂, WSi₂, W(SiAl)₂, Ti₇Si₁₂Al₅ and Pd₄SiAl₃.

14. A method according to claim 5, wherein the metal layer comprises a material selected from the group consisting of Mo, W, Pt, Cr, Ti and Co.

9. A method for manufacturing a semiconductor device comprising the steps of:

forming a semiconductor film over a substrate;

crystallizing the semiconductor film by irradiating a laser light;

forming a silicon oxide film in contact with the crystalline semiconductor film by using organic silane;

forming a gate electrode in contact with the gate insulating film;

forming a metal layer in contact with a portion of the crystalline semiconductor film; and

forming a metal silicide layer by reacting the metal layer with the portion of the crystalline semiconductor film by heating.

10. A method according to claim 9, wherein the method further comprises a step of removing a portion of the metal layer which did not react with the portion of the crystalline semiconductor film.

11. A method according to claim 9, wherein the organic silane is TEOS.

12. A method according to claim 9, wherein the metal silicide layer comprises a material selected from the group consisting of TiSi, TiSi₂, MoSi₂, WSi₂, W(SiAl)₂, Ti₇Si₁₂Al₅ and Pd₄SiAl₃.

15. A method according to claim 9, wherein the metal layer comprises a material selected from the group consisting of Mo, W, Pt, Cr, Ti and Co.

16. A method for manufacturing a semiconductor device comprising the steps of:

forming a silicon oxide film in contact with a semiconductor film by using organic silane;

forming a gate electrode in contact with the gate insulating film;

forming a metal layer in contact with a portion of the semiconductor film; and

forming a metal silicide layer by reacting the metal layer with the portion of the semiconductor film by irradiating a laser light.

17. A method according to claim 16, wherein the method further comprises a step of removing a portion of the metal layer which did not react with the portion of the semiconductor film.

18. A method according to claim 16, wherein the organic silane is TEOS.

19. A method according to claim 16, wherein the metal layer comprises a material selected from the group consisting of Mo, W, Pt, Cr, Ti and Co.

20. A method according to claim 16, wherein the metal suicide layer comprises a material selected from the group consisting of TiSi, TiSi₂, MoSi₂, WSi₂, W(SiAl)₂, Ti₇Si₁₂Al₅ and Pd₄SiAl₃.

21. A method for manufacturing a semiconductor device comprising the steps of:

forming a silicon oxide film in contact with a semiconductor film by using organic silane;

forming a gate electrode in contact with the gate insulating film;

forming a metal layer in contact with a portion of the semiconductor film; and

forming a metal silicide layer by reacting the metal layer with the portion of the semiconductor film by irradiating an infrared light.

22. A method according to claim 21, wherein the method further comprises a step of removing a portion of the metal layer which did not react with the portion of the semiconductor film.

23. A method according to claim 21, wherein the organic silane is TEOS.

24. A method according to claim 21, wherein the metal layer comprises a material selected from the group consisting of Mo, W, Pt, Cr, Ti and Co.

25. A method according to claim 21, wherein the metal silicide layer comprises a material selected from the group consisting of TiSi, TiSi₂, MoSi₂, WSi₂, W(SiAl)₂, Ti₇Si₁₂Al₅ and Pd₄SiAl₃.

26. A method for manufacturing a semiconductor device comprising the steps of:

forming a silicon oxide film in contact with a semiconductor film by using organic silane;

forming a gate electrode in contact with the gate insulating film;

forming a metal layer in contact with a portion of the semiconductor film; and

forming a metal silicide layer by reacting the metal layer with the portion of the semiconductor film by heating.

27. A method according to claim 26, wherein the method further comprises a step of removing a portion of the metal layer which did not react with the portion of the semiconductor film.

28. A method according to claim 26, wherein the organic silane is TEOS.

29. A method according to claim 26, wherein the metal layer comprises a material selected from the group consisting of Mo, W, Pt, Cr, Ti and Co.

30. A method according to claim 26, wherein the metal suicide layer comprises a material selected from the group consisting of TiSi, TiSi₂, MoSi₂, WSi₂, W(SiAl)₂, Ti₇Si₁₂Al₅ and Pd₄SiAl₃.