High Ion/Ioff SOI MOSFET using body voltage control

• US 7,109,532 B1
• Filed: 12/23/2003
• Issued: 09/19/2006
• Est. Priority Date: 12/23/2003
• Status: Expired due to Fees

• Current Assignee: T-Ram, LLC
• Original Assignee: T-RAM Semiconductor, Inc.
• Inventors: Nemati, Farid, Robins, Scott, Lee, Zachary K.
• Primary Examiner(s): QUACH, TUAN N
• Application Number:
  US10/746,758
• Time in Patent Office: 1,001 Days
• Field of Search: 257/107, 257/133, 257347-351
• US Class Current: 257/133
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors

Abstract

A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.

Claims

1. A silicon-on-insulator (SOI) device, comprising:

a body region disposed between source and drain regions in a layer of silicon over an insulator,

a gate disposed in insulated relationship to the body region and operable under bias to effect a conductivity within the body region;

the body region comprising a channel portion proximate the gate and a floating body portion more distal the gate; and

an extra dopant region against one of the source and the drain regions, the extra dopant region of a conductivity type opposite that of the one of the source and the drain regions;

wherein the extra dopant region is separate and non-contiguous to the body region and separated therefrom by at least a portion of the one of the source and the drain regions; and

the body region comprises a doping profile to assist the injection of carriers into the floating body portion of the body region.

2. The device of claim 1, further comprising:

a memory cell;

the source, body and drain regions in combination with the gate defining at least in part an access transistor by which to access the memory cell.

3. The device of claim 2, in which the one of the source and the drain regions comprises silicide at a surface of the layer of silicon for imparting a recombination rate sufficient to prevent interlatching of the access transistor during the injection of carriers into the floating body portion.

4. The device of claim 3, in which the body region, the one of the source and the drain regions and the extra dopant region comprise doping configurations to define a gain for an inherent bipolar device of a magnitude sufficient to assist the injection of carriers into the floating body portion and small enough to avoid interlatching.

5. The device of claim 2, in which the one of the source and the drain regions comprises:

a lower portion proximate the insulator of a first doping concentration; and

an upper portion proximate a surface of the layer of silicon of a second doping concentration;

wherein the first doping concentration is greater than the second doping concentration by at least a factor of two.

6. The device of claim 2, in which the one of the source and the drain regions comprises:

a lower portion proximate the insulator of a first doping concentration; and

an upper portion proximate a surface of the layer of silicon of a second doping concentration;

wherein the second doping concentration is sufficiently light to impart a gain to an inherent bipolar device for effecting carrier transport properties thereto as to define at least in part and collectively by the body and the drain regions of the access transistor and the extra doped region;

the carrier transport gain as attributable to the inherent bipolar device is further effected with magnitude to assist the injection of carriers to the floating body portion of the body region yet sufficiently small to prevent inter-latching of the access transistor during device operation.

7. A semiconductor-on-insulator (SOI) device, comprising:

a layer of semiconductor material over an insulator;

a body region disposed between source and drain regions in the layer of semiconductor material;

a gate disposed in insulated relationship to the body region and operable under bias to effect a conductivity within the body region;

the body region comprising a channel portion proximate the gate and a floating body portion more distal the gate;

an extra dopant region against one of the source and the drain regions and of a conductivity type opposite that of the one of the source and the drain regions;

the one of the source and the drain regions disposed between the extra dopant region and the body region comprising a doping profile to assist injection of carriers into the floating body portion of the body region; and

a thyristor for a memory cell defined at least in part within the layer of semiconductor material;

wherein the source, the body and the drain regions in combination with the gate define at least in part an access transistor by which to access the thyristor; and

the extra dopant region defines part of the thyristor.

8. The device of claim 7, in which

the thyristor comprises anode/cathode emitter, first base, second base, and cathode/anode emitter regions respectively in the layer of semiconductor material;

the anode/cathode emitter of the thyristor is in common with the one of the source and the drain regions of the access device;

the extra dopant region is in common with the first base region of the thyristor; and

the device further comprises a capacitor electrode capacitively coupled through dielectric to the first base region of the thyristor.

9. A semiconductor-on-insulator (SOI) device, comprising:

a layer of semiconductor material over an insulator for an SOI structure;

a thyristor comprising anode-emitter, N-base, P-base, and cathode-emitter regions in the layer of semiconductor material;

a MOSFET transistor disposed electrically in series with the thyristor, the MOSFET transistor comprising a body region disposed between source and drain regions in the semiconductor material; and

a gate electrode disposed in insulated relationship to the body region and configured to receive a bias signal operable to effect a conductivity within the body region;

wherein the body region comprises a channel portion proximate the gate electrode and a floating body portion distal the gate electrode; and

the cathode-emitter region for the thyristor is formed in common with one of the source and the drain regions to the MOSFET transistor, and comprises a doping profile to assist injection of carriers into the floating body portion of the body region.

10. The device of claim 9, in which the one of the source and the drain regions further comprises a length between the body region and an extra dopant region of the P-base region to the thyristor that is operable collectively with the doping profile thereof for the enabling of the carrier injection into the floating body portion of the body region.

11. The device of claim 9, further comprising a capacitor electrode capacitively coupled through dielectric to the P-base region of the thyristor.

12. The device of claim 11, further comprising a bias circuit configured to bias the floating body portion of the body region of the MOSFET transistor.

13. The device of claim 9, in which the one of the source and the drain regions in common with the cathode-emitter region comprises:

a lower region proximate the insulator of a first doping concentration; and

an upper region proximate a surface of the layer of semiconductor material of a second doping concentration;

wherein the first doping concentration is greater than the second doping concentration by at least a factor of two.

14. The device of claim 9, in which the one of the source and the drain regions in common with the cathode-emitter region comprises:

a lower region proximate the insulator of a first doping concentration; and

an upper region proximate a surface of the layer of semiconductor material of a second doping concentration;

wherein the second doping concentration is sufficiently light to impart gain to a carrier transport property for an inherent bipolar device defined at least in part and collectively by the body and the drain regions of the MOSFET transistor and the P-base region of the thyristor;

the carrier transport gain is attributable to the inherent bipolar device further effected with magnitude sufficient to assist the carrier injection into the floating body portion of the body region yet sufficiently small to prevent inter-latching of the MOSFET during device operation.