Electrostatic discharge protection device

• US 7,109,533 B2
• Filed: 03/24/2003
• Issued: 09/19/2006
• Est. Priority Date: 03/25/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Kodama, Noriyuki
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US10/394,179
• Publication Number:
  US 20030179523A1
• Time in Patent Office: 1,275 Days
• Field of Search: None
• US Class Current: 257/173
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Abstract

There is provided an electrostatic discharge protection device comprising a P conductive type first P well region 101 formed in a P type epitaxial layer 31 being deposited on a surface of a P+ substrate 30 having a prescribed thickness, an N conductive type first N well 101 a periphery thereof being brought into direct contact with and surrounded by a first P well region 101, P conductive type first P diffusion regions 121a and 121b, a P conductive type third P diffusion region 125, and an N conductive type second N diffusion region 223 arranged within a first P well region 101, and a P conductive type second P diffusion region 123 and an N conductive type first N diffusion region 221 arranged within a first N well 201.

Claims

1. An electrostatic discharge protection device comprising:

a P conducive type first P well region formed in a P conductive type semiconductor layer of a semiconductor substrate having said P conductive type semiconductor layer having a prescribed thickness on a surface thereof;

an N conductive type first N well, a periphery thereof being surrounded by said first P well region, a second N diffusion region, P conductive type first P diffusion regions, and a P conductive type third P diffusion region arranged within said first P well; and

a P conductive type second P diffusion region and N conductive type first N diffusion region arranged in said first N well,

wherein said second N diffusion region is arranged between said first P diffusion regions and said first N well by being opposed thereto, a first boundary side constituting a boundary between said first N well and said first P well region and opposed to said second N diffusion region includes a first recessed portion incised on a side of said first N well,

wherein said second P diffusion region is arranged between said first N diffusion region and said first boundary side, said third P diffusion region is arranged between said second N diffusion region and said first boundary side such that at least a part thereof is brought into said first recessed portion,

wherein said first N diffusion region is connected to a high potential side electric source, both of said second N diffusion region and said first P diffusion regions are connected to a low potential side electric source, said second P diffusion region is connected to a desired external connection electrode, and said third P diffusion region is connected to an output end of a first trigger device an input end thereof being connected to said external connection electrode.

21. The electrostatic discharge protection device according to claim 1, wherein said first trigger device is an N channel type field effect transistor by connecting a gate electrode to a low potential side electric source interconnection, one end of source drain passage is connected to said external connection electrode, and other end constitutes an output end of corresponding first trigger device.

22. The electrostatic discharge protection device according to claim 1, wherein said first trigger device is a first diode row by connecting all of m pieces (however, m denotes positive integer) of PN junction diode in series by constituting such that a cathode of a preceding step is connected to an anode of a following step, an anode of an initial step is connected to said external connection electrode, and a cathode of a final step constitutes an output end of corresponding first trigger device.

24. The electrostatic discharge protection device according to claim 1, wherein said second trigger device includes a N channel type field effect transistor (hereinafter, referred to as NMOS) and PN junction diode, a gate electrode of said NMOS is connected to a low potential side electric source interconnection and a source drain passage are connected between said external connection electrode and the anode of said PN junction diode, and the cathode and anode of said PN junction diode are constituted as a first output end and a second output end of respective corresponding second trigger device.

25. The electrostatic discharge protection device according to claim 1, wherein said first N diffusion region and said second P diffusion region are arranged by being brought into direct contact.

26. The electrostatic discharge protection device according to claim 1, wherein said first N diffusion region and said second P diffusion region are arranged by isolating therefrom.

29. The electrostatic discharge protection device according to claim 1, wherein said semiconductor substrate is fabricated by depositing a prescribed thickness of a P conductive type epitaxial layer on a surface of a P type substrate having resistivity of 10 Ω

·

cm or less.

2. An electrostatic discharge protection device comprising:

a P conductive type second P well and P conductive type first P diffusion regions formed in a P type semiconductor layer of a semiconductor substrate having the P conductive type semiconductor layer having a prescribed thickness on a surface thereof;

an N conductive type second N well being brought into direct contact with the second P well;

P conductive type third P diffusion regions and N conductive type second N diffusion regions arranged within the second P well; and

a P conductive type second P diffusion region and an N conductive type first N diffusion region arranged within the second N well,

wherein said third P diffusion regions are arranged at k portions (where k denotes an integer of 2 or more), said first P diffusion regions and said second N diffusion regions are arranged respectively at (k+1) portions,

wherein said first P diffusion regions are arranged at (k+1) portions on a first straight line while are brought into direct contact with said second P well at an outside of said second P well, and said second N diffusion regions are arranged at (k+1) portions on a second straight line being in parallel with said first straight line,

wherein a second boundary side constituting a boundary where said second P well and said second N well is brought into contact with each other includes first recessed portions disposed in k portions incised on a side of the second N well,

wherein said second P diffusion regions are arranged between the first N diffusion region and said second boundary side,

wherein said second N diffusion regions of (k+1) portions are arranged respectively between a portion said second N well of the second boundary side constituting projected portions and said first P diffusion regions and by corresponding the single second N diffusion region to said single first P diffusion region,

wherein by corresponding, said single first recessed portion to said single third P diffusion region at least a part of respective third P diffusion regions is arranged to enter said first recessed portion,

wherein said first N diffusion region is connected to a high potential side electric source, both of said second N diffusion regions and said first P diffusion regions are connected to a low potential side electric source, said second P diffusion region is connected to a desired external connection electrode, and said third P diffusion regions are connected to output ends of a first trigger device an input end thereof being connected to said external connection electrode.

3. The electrostatic discharge protection device according to claim 2, wherein said third P diffusion regions further have overlapped portions including cases where being brought into contact with a straight line extending along a boundary opposed to said second N well of said second N diffusion regions.

4. An electrostatic discharge protection device comprising:

a P conductive type first P well region formed on a P type semiconductor layer of a semiconductor substrate having the P conductive type semiconductor layer having a prescribed thickness on a surface thereof;

a plurality of N conductive type third N wells peripheries thereof being surrounded by the first P well region;

a P conductive type first P diffusion regions, a P conductive type third P diffusion region, and N conductive type second N diffusion region arranged in the first P well region; and

P conductive type second P diffusion regions and N conductive type first N diffusion regions respectively arranged within the third N wells,

wherein said plurality of third N wells are arranged on a first straight line by being isolated therefrom,

wherein said second N diffusion region is arranged between said third N wells and said first P diffusion regions by being isolated from and opposed to any of the plurality of said third N wells,

wherein said first N diffusion regions and said second P diffusion regions are arranged respectively in said third N wells by aligning in a direction orthogonal to a direction of a first straight line so that said second P diffusion regions come closer to said second N diffusion region,

wherein said third P diffusion region is arranged between said plurality of third N wells,

wherein said first N diffusion regions are connected to a high potential side electric source, both of the second N diffusion region and said first diffusion regions are connected to a low potential side electric source, said second P diffusion regions are connected to desired external connection electrodes, and said third P diffusion region is connected to an output end of a first trigger device an input end thereof being connected to said external connection electrode.

5. The electrostatic discharge protection device according to claim 4, wherein said third P diffusion region is arranged such that, there being existed a straight line in a direction of said first straight line crossing simultaneously with said second P diffusion regions.

6. An electrostatic discharge protection device comprising:

a P conductive type first P well region formed in a P type semiconductor layer of a semiconductor substrate having the P conductive type semiconductor layer having a prescribed thickness on the surface thereof;

a N conductive type fourth N well a periphery thereof being surrounded by the first P well region;

a P conductive type first P diffusion region and N conductive type second N diffusion region arranged within the first P well region;

a P conductive type second P diffusion region and N conductive type first N diffusion region arranged within the fourth N well; and

a plurality of first blank portions being exposed the first P well region provided in the second N diffusion region, and third P diffusion regions arranged in the first blank portions,

wherein said fourth N well is arranged between said first P diffusion region and said second N diffusion region by being opposed thereto and isolated therefrom,

wherein said first N diffusion region and said second P diffusion region are arranged side by side so that said first N diffusion region comes closer to a side of said first P diffusion region, and said second P diffusion region comes closer to a side of the second N diffusion region,

wherein said first blank portions are arranged along a third boundary side constituting a boundary between said second N diffusion region and said first P well region and, by being opposed to said fourth N well and isolated therefrom,

wherein said first N diffusion region is connected to a high potential side electronic source, both of said second N diffusion region and said first P diffusion region are connected to a low potential side electronic source, and the second P diffusion region is connected to a desired external connection electrode, and said third P diffusion regions are connected to an output end of a first trigger device an input end thereof being connected to the external connection electrode.

7. The electrostatic discharge protection device according to claim 6, wherein contact holes connected to said second N diffusion region are formed in a region on an opposite side to a side of said third boundary side with respect to a straight line in a direction in parallel with said third boundary side passing through a boundary on a side of said third boundary side of said first blank portion.

8. An electrostatic discharge protection device comprising:

a P conductive type third P well region formed in a P type semiconductor layer of a semiconductor substrate having the P conductive type semiconductor layer having a prescribed thickness on a surface thereof;

an N conductive type third N diffusion region and a N conductive type fourth N diffusion region;

a gate region;

an N conductive type fourth N well a periphery thereof being surrounded by the third P well region;

a P conductive type first P diffusion region and a P conductive type third P diffusion region being arranged within the third P well region;

a P conductive type second P diffusion region and a N conductive type first N diffusion region being arranged within the fourth N well; and

a second N diffusion region arranged by striding over a fourth boundary side constituting a boundary between the third P well region and a P type semiconductor layer region,

wherein said fourth N well is arranged between said first P diffusion region and said second N diffusion region being opposed thereto and directions of respective boundaries opposing thereto being in parallel with said fourth boundary side,

wherein said first N diffusion region and said second P diffusion region are arranged side by side so that said first N diffusion region coming closer to a side of said first P diffusion region and said second P diffusion region coming closer to a side of the second N diffusion region,

wherein the second N diffusion region includes respectively a plurality of projected portions reaching to the P type semiconductor layer region and a plurality of recessed portions reaching to said third P well region on a boundary of on opposite side of a third boundary side constituting said boundary between said second N diffusion region and said third P well region and opposed to said fourth N well,

wherein said third P diffusion regions are arranged in said third P well region portions of said respective recessed portions, said third N diffusion region is arranged by opposing to a boundary on an opposite side of the third boundary side of said second N diffusion region, said gate region is arranged by being brought into contact with a boundary on an opposite side of said boundary opposed to the second N diffusion region of said third N diffusion region, the fourth N diffusion region is arranged by being opposed to said third N diffusion region via said gate region and being brought into contact with said gate region, and said boundary of said third N diffusion region opposed to said second N diffusion region include projected portions being brought into direct contact with said third P diffusion regions by passing through the recessed portions,

wherein said first N diffusion region is connected to a high potential side electric source, all of said second N diffusion region, said first P diffusion region, and said gate electrode provided in said gate region are connected to a low potential side electric source, and both of said second P diffusion region and said fourth P diffusion region are connected to desired external connection electrodes. In that case, said boundary where said third N diffusion region and said fourth N diffusion region are respectively brought into contact with said gate region may constitute a straight line shape along a direction of said fourth boundary side.

9. The electrostatic discharge protection device according to claim 8, wherein a boundary being brought into contact respective said third N diffusion region and said fourth N diffusion region with said gate region is in a shape of a straight line along a direction in said fourth boundary side.

10. An electrostatic discharge protection device comprising:

a P conductive type first P well region formed in a P type semiconductor layer of a semiconductor substrate having the P conductive type semiconductor layer having a prescribed thickness on a surface thereof;

an N conductive type fifth N well a periphery thereof being surrounded by the first P well region;

a P conductive type fourth P well a periphery thereof being surrounded by the fifth N well;

a P conductive type first P diffusion region and a N conductive type second N diffusion region arranged within the first P well region;

a P conductive type second P diffusion region and a N conductive type first N diffusion region arranged within the fifth N well; and

a third P diffusion region arranged within the fourth P well,

wherein said second N diffusion region is arranged between said fifth N well and said first P diffusion region by being opposed thereto,

wherein said second P diffusion region is arranged between said first N diffusion region and the second N diffusion region by being opposed thereto,

wherein said second P diffusion region surrounds a periphery of said fourth P well,

wherein the first N diffusion region is connected to a high potential side electric source, both of said second N diffusion region and said first P diffusion region are connected to a low potential side electric source, said second P diffusion region is connected to a desired external connection electrode, and said third P diffusion region is connected to an output end of a first trigger device an input end thereof being connected to said external connection electrode.

11. An electrostatic discharge protection device comprising:

a P conductive type first P well region formed on the P type semiconductor layer of a semiconductor substrate having the P conductive type semiconductor layer having a prescribed thickness on a surface thereof;

an N conductive type sixth N well and a N conductive type seventh N well peripheries thereof being surrounded respectively by the first P well regions;

a P conductive type first P diffusion region and a N conductive type second N diffusion region arranged within the first P well region;

a second P diffusion region and a first N diffusion region arranged within the sixth N well;

a fourth P diffusion region arranged within the seventh N well,

wherein said sixth N well is arranged between said first P diffusion region and said second N diffusion region by opposing thereto,

wherein said first N diffusion region is arranged between said first P diffusion region and the second P diffusion region by opposing thereto,

wherein said second N diffusion region includes a N—

N overlapped portion overlapped with said seventh N well and is arranged by being opposed the N—

N overlapped portion to said fourth P diffusion region,

wherein the first N diffusion region is connected to a high potential side electric source, both of said second N diffusion region and said first P diffusion region are connected to a low potential side electric source, said second P diffusion region is connected to a desired external connection electrode, and said fourth P diffusion region is connected to an output end of a first trigger device an input end thereof being connected to said external connection electrode.

12. The electrostatic discharge protection device according to claim 11, wherein said second N diffusion region has a boundary opposed to said sixth N well constituting a straight line shaped straight line side, a boundary on an opposite side to said straight line side constituting a first irregularity side having a comb shaped irregularity, and a projected portion of said first irregularity side constitutes said N—

N overlapped portion overlapped with said seventh P well, said fourth P diffusion region is arranged opposed to said first irregularity side, a boundary of said fourth P diffusion region opposed to said first irregularity side constituting a second irregularity side having a comb shaped irregularity, and said second N diffusion region and said fourth P diffusion region are arranged such that one projected portion of said first irregularity side and said second irregularity side being brought into and brought in mesh with other recessed portion thereof.

13. An electrostatic discharge protection device comprising:

a P conductive type first P well region formed in a P type semiconductor layer of a semiconductor substrate having the P conductive type semiconductor layer having a prescribed thickness on a surface thereof,

an N conductive type sixth N well and a N conductive type sixth N well respective peripheries thereof are surrounded by the first P well region;

a P conductive type first P diffusion region and P conductive type third P diffusion regions and an N conductive type second N diffusion region arranged within the first P well region;

a second P diffusion region and a first N diffusion region arranged within the sixth N well; and

a fourth P diffusion region arranged within the seventh N well,

wherein said sixth N well is arranged between said first P diffusion region and said second N diffusion region,

wherein said first N diffusion region is arranged between said first P diffusion region and said second P diffusion region by opposing thereto,

wherein a boundary of said second N diffusion region opposing to said sixth N well is a straight line shaped straight line side, a boundary on an opposite side to the straight line side constitutes a first irregularity side including a comb shaped irregularity, and a projected portion of said first irregularity side constitutes an N—

N overlapped portion overlapped with said seventh N well,

wherein said fourth P diffusion region is arranged opposed to said first irregularity side,

wherein a boundary of said fourth P diffusion region opposed to said first irregularity side constitutes a second irregularity side having a comb shaped irregularity, and said second N diffusion region and said fourth P diffusion region are arranged such that one projected portion of said first irregularity side and said second irregularity side being brought into and brought in mesh with other recessed portion thereof,

wherein said third P diffusion regions are arranged within said first P well region of respective recessed portion of said first irregularity side,

wherein said first N diffusion region is connected to a high potential side electric source, both of said second N diffusion region and said first P diffusion region are connected to a low potential side electric source, said second P diffusion region is connected to a desired external connection electrode, and said third P diffusion regions are connected to a first output end of a second trigger device having said first output end and a second output end an input end thereof being connected to an external connection electrode, and said fourth P diffusion region is connected to said second output end.

14. The electrostatic discharge protection device according to claim 13, wherein said the EDS protection device has connection interconnection connecting respective said third P diffusion regions each other.

23. The electrostatic discharge protection device according to claim 13, wherein said second trigger device is a second diode row by connecting all of (m+1) pieces (however, m denotes a positive integer) of PN junction diode in series by constituting such that a cathode of a preceding step is connected to an anode of a following step, an anode of an initial step is connected to said external connection electrode, and a cathode of a final step and a cathode at m steps constitute a first output end and a second output end of respectively corresponding second trigger device.

15. An electrostatic discharge protection device comprising:

a P conductive type first P well region formed in a P type semiconductor layer of said semiconductor substrate having said P conductive type semiconductor layer having a prescribed thickness on a surface thereof;

an N conductive type eighth N well and an N conductive type ninth N well respective peripheries thereof are surrounded by said first P well region;

an N conductive type second N diffusion region arranged within said first P well region; and

a second P diffusion region and a first N diffusion region arranged within said eighth N well, and a fourth P diffusion region arranged in said ninth N well,

wherein said second N diffusion region is arranged between said eighth N well and said ninth N well,

wherein a boundary of said second N diffusion region opposed to said eighth N well constitutes a straight line shaped straight line side, a boundary on an opposite side to said straight line side constitutes a first irregularity side having a comb shaped irregularity, and a projected portion of said first irregularity side constitutes an N—

N overlapped portion overlapped with said ninth N well,

wherein a boundary where said first N diffusion region and said second P diffusion region opposed to each other has an irregular shape and one projected portion is entered into and brought in mesh with other recessed portion,

wherein said second P diffusion region is arranged between said first N diffusion region and said second N diffusion region by being isolated therefrom, said fourth P diffusion region is arranged by opposing to said first irregularity side, a boundary of said fourth P diffusion region opposed to said first irregularity side constitutes a second irregularity side having a comb shaped irregularity,

wherein said second N diffusion region and said second irregularity side of said fourth P diffusion region are arranged such that one projected portion of said first irregularity side and said second irregularity side being entered into and brought in mesh with other recessed portion thereof,

wherein said first N diffusion region is connected to a high potential side electric source, said second N diffusion region is connected to a low potential side electric source, said second P diffusion region is connected to a desired external connection electrode, and said fourth P diffusion region is connected to an output end of a first trigger device an input end thereof being connected to said external connection electrode.

16. An electrostatic discharge protection device comprising:

a P conductive type first P well region formed in a P type semiconductor layer of a semiconductor substrate having the P conductive type semiconductor layer having a prescribed thickness on a surface thereof;

an N conductive type tenth N well and a plurality of N conductive type third N wells respective peripheries thereof being surrounded by the first P well region;

first P diffusion regions, third P diffusion regions and fifth P diffusion regions of respective P conductive types and N conductive type second N diffusion regions and a fifth N diffusion region arranged within the first P well region, and a P conductive type second P diffusion region and N conductive type first N diffusion region respectively arranged in the third N well; and

a P conductive type sixth P diffusion region and N conductive type sixth N diffusion region arranged within the tenth N well,

wherein a plurality of third N wells are arranged in a straight line shape,

wherein two directions orthogonal to each other constitute respectively X direction and Y direction, when an a direction of arranging of the plurality of third N wells constitute said Y direction,

wherein said tenth N well is arranged between said third N wells, said second N diffusion regions are arranged between said third N wells and said first P diffusion regions and by being isolated from and opposed to said third N wells in said X direction, said first N diffusion regions and said second P diffusion regions are arranged side by side in X direction within respective third N wells by setting said second P diffusion regions on a side of said second diffusion regions, said sixth N diffusion region and said sixth P diffusion region are arranged side by side in said X direction within the tenth N well by setting said sixth P diffusion region on a side of said fifth N diffusion region, and said first P diffusion regions, and being isolated from and opposed to said tenth N well in X direction, said third P diffusion regions arranged between respective third N wells and tenth N well, and the fifth P diffusion regions are arranged on an opposite side to said third P diffusion regions by sandwiching said third N wells in said Y direction.

wherein said first N diffusion region and said sixth N diffusion region are connected to high potential electric sources, both of said first P diffusion regions and said second N diffusion regions are connected to a low potential side electric source, the second P diffusion regions and said sixth P diffusion region are connected to desirable external connection electrodes, said third P diffusion regions is connected to an output end of a first trigger device input end thereof being connected to said external connection electrode, and said fifth N diffusion region is connected to said fifth P diffusion regions.

17. The electrostatic discharge protection device according to claim 16, wherein said third P diffusion region and fifth P diffusion region are arranged on a same straight line of said Y direction.

18. The electrostatic discharge protection device according to claim 16, wherein said third P diffusion region is arranged such that when a straight line passing through an end portion of said X direction of respective said third P diffusion region is extended in said Y direction, a straight line passing through said one end portion crosses said tenth N well, and a straight line passing through said other end portion crosses said fifth N diffusion region.

19. The electrostatic discharge protection device according to claim 16, wherein said fifth P diffusion region is arranged such that when a straight line passing through an end portion in said X direction of said respective fifth P diffusion region is extended in said Y direction, a straight line passing through said one end portion crosses said third N well, a straight line passing through said other end portion crosses said second N diffusion region.

20. The electrostatic discharge protection device according to claim 16, wherein each of said first P diffusion regions is arranged in a central portion of said Y direction of each said second N diffusion regions opposed to said first P diffusion regions in said X direction.

27. The electrostatic discharge protection device according to claim 16, wherein said first N diffusion region and said second P diffusion region are arranged by being brought into direct contact with and said sixth N diffusion region and said fifth P diffusion region are arranged by being brought into direct contact with each other.

28. The electrostatic discharge protection device according to claim 16, wherein said first N diffusion region and said second P diffusion region are arranged by being isolated therefrom and said sixth N diffusion region and said fifth P diffusion region area arranged by being isolated therefrom.

30. An electrostatic discharge protection device comprising:

a P type semiconductor substrate;

a first N type well region fabricated on a surface of said P type semiconductor substrate;

a first P type region fabricated in said first N type well region;

a second N type region fabricated on said surface of said P type semiconductor substrate;

a silicon controlled rectifier having said first P type region as an anode region, said second N type region as an cathode region;

a controlled region controlling a first current flowing from said anode region to said cathode region;

wherein, said controlled region control said first current so as to control said first current uniformly flowing within said semiconductor substrate;

wherein, said controlled region is formed within at least one of nearest position of said anode region and said cathode region.

31. An electrostatic discharge protection device according to claim 30, wherein said controlled region is formed within a position on said surface of said P type semiconductor substrate so as to control said first current not flowing under said cathode region.

32. An electrostatic discharge protection device according to claim 30, further comprising a first trigger tap region controlling a first trigger current turning on a lateral NPN bipolar transistor formed in said silicon controlled rectifier;

wherein, said first trigger tap region control said first trigger current so as to control said first trigger current uniformly flowing within said semiconductor substrate.

33. An electrostatic discharge protection device according to claim 32, further comprising a second trigger tap region controlling a second trigger current turning on a vertical PNP bipolar transistor formed in said silicon controlled rectifier;

wherein, said second trigger tap region control is formed in said on said surface of said P type semiconductor substrate;

wherein, said second trigger tap region control said second trigger current so as to control said second trigger current uniformly flowing within said semiconductor substrate.