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Architecture for vertical transistor cells and transistor-controlled memory cells

  • US 7,109,544 B2
  • Filed: 02/13/2004
  • Issued: 09/19/2006
  • Est. Priority Date: 02/14/2003
  • Status: Expired due to Fees
First Claim
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1. The vertical transistor architecture, comprising:

  • an array of vertical transistor cells formed in a substrate and arranged in a transistor plane, in rows in an x direction, and in columns in a y direction perpendicular to the x direction;

    an array of active trenches, wherein the active trenches separate the rows of transistor cells; and

    an array of isolation trenches, wherein the isolation trenches separate the columns of transistor cells;

    wherein active regions at least of transistor cells which are adjacent to one another in the x direction are connected to one another, whereby a charge carrier transport is made possible between the active regions of transistor cells which are adjacent in the x direction;

    wherein the vertical transistor cells comprise;

    respective lower source/drain connection region;

    respective upper source/drain connection regions arranged above the lower source drain regions;

    respective conductive channels disposed between the upper and lower source/drain connection regions; and

    respective gate electrodes insulated from the active regions by a gate dielectric;

    wherein the active regions are in each case sections of a contiguous layer body, wherein the continuous body is patterned at least by the isolation trenches in an upper region, and wherein the contiguous body in a lower region connects the active regions of transistor cells that are adjacent to one another at least in the x direction;

    wherein the vertical transistor architecture further comprises a plurality of layer bodies deposed in the transistor cell array in each case separated from one another by the active trenches.

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