Architecture for vertical transistor cells and transistor-controlled memory cells

• US 7,109,544 B2
• Filed: 02/13/2004
• Issued: 09/19/2006
• Est. Priority Date: 02/14/2003
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Manger, Dirk, Schloesser, Till, Goebel, Bernd
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US10/777,128
• Publication Number:
  US 20050001257A1
• Time in Patent Office: 949 Days
• Field of Search: 257/296, 257/301, 257/302
• US Class Current: 257/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

In a substrate vertical transistor cells are formed and are arranged, in a transistor cell array, row by row in an x direction and column by column in a y direction. Lower source/drain regions of the transistor cells are connected to a common connection plate. Upper source/drain regions of the transistor cells impart a contact connection for instance to a storage capacitor of a DRAM memory cell. Active trenches running between the transistor cells with word lines are formed along the x direction. The word lines form gate electrodes in sections. A potential at the gate electrode controls a conductive channel in an active region arranged in each case between the upper and the lower source/drain connection region. According to the invention, the active regions of adjacent transistor cells are sections of a contiguous layer body and are connected to one another. An accumulation of charge carriers in the active region and floating body effects are avoided without increasing the area requirement of a transistor cell.

Claims

1. The vertical transistor architecture, comprising:

an array of vertical transistor cells formed in a substrate and arranged in a transistor plane, in rows in an x direction, and in columns in a y direction perpendicular to the x direction;

an array of active trenches, wherein the active trenches separate the rows of transistor cells; and

an array of isolation trenches, wherein the isolation trenches separate the columns of transistor cells;

wherein active regions at least of transistor cells which are adjacent to one another in the x direction are connected to one another, whereby a charge carrier transport is made possible between the active regions of transistor cells which are adjacent in the x direction;

wherein the vertical transistor cells comprise;

respective lower source/drain connection region;

respective upper source/drain connection regions arranged above the lower source drain regions;

respective conductive channels disposed between the upper and lower source/drain connection regions; and

respective gate electrodes insulated from the active regions by a gate dielectric;

wherein the active regions are in each case sections of a contiguous layer body, wherein the continuous body is patterned at least by the isolation trenches in an upper region, and wherein the contiguous body in a lower region connects the active regions of transistor cells that are adjacent to one another at least in the x direction;

wherein the vertical transistor architecture further comprises a plurality of layer bodies deposed in the transistor cell array in each case separated from one another by the active trenches.

2. The vertical transistor architecture of claim 1, wherein the gate electrodes are arranged in the active trenches and wherein the gate electrodes of transistor cells which are adjacent in the x direction are connected to one another and form sections of word lines.

3. The vertical transistor architecture of claim 1, wherein the lower source/drain connection regions are in each case connected to a contiguous connection plate.

4. The vertical transistor architecture of claim 1, wherein the lower source/drain connection regions are in each case sections of a connection plate that is patterned at least in an upper region and is contiguous in a lower region.

5. The vertical transistor architecture of claim 1, wherein the layer bodies are lengthened in each case row by row into a connection array adjoining the transistor cell array.

6. The vertical transistor architecture of claim 5, wherein the layer bodies are connected to one another in the region of the connection array.

7. The vertical transistor architecture of claim 1, wherein the layer bodies are connected to a structure having a substrate potential.

8. The vertical transistor architecture of claim 1, wherein a connection plate is patterned in an upper region by the active trenches extending along the x axis, wherein the lower source/drain connection regions are formed in the upper region of the connection plate in each case below the active regions, wherein the isolation trenches have a smaller depth than the active trenches, and wherein the layer bodies are fanned contiguously row by row in each in a lower region below the isolation trenches.

9. The vertical transistor architecture of claim 8, wherein the isolation trenches are filled with an insulator material.

10. The vertical transistor architecture of claim 1, wherein the isolation trenches and the active trenches have an essentially identical depth, wherein the lower source/drain connection regions are formed in each case in an upper region of the connection plate below the active trenches, and wherein the layer bodies are formed contiguously row by row in each case below the active regions and are separated from one another by the source/drain connection regions in a lower region.

11. The vertical transistor architecture of claim 1, wherein an upper region of the connection plate is patterned in the x direction and in the y direction, wherein a lower source/drain connection region delimited in the x direction and the y direction is in each case formed in the upper region of the connection plate, and wherein the active regions of transistor cells which are adjacent in the x direction and the y direction are formed contiguously by a single layer body which is patterned by the lower source/drain connection regions.

12. The vertical transistor architecture of claim 11, wherein the layer body is lengthened into a connection array adjoining the transistor cell array.

13. The vertical transistor architecture of claim 11, wherein the layer body is connected to a structure having a substrate potential.

14. The vertical transistor architecture of claim 1, wherein the active regions of the transistor cells have a cross-sectional area of essentially F² relative to a production-dictated minimum feature size F parallel to the transistor plane, and wherein the area requirement of a transistor cell is essentially 4 F².

15. The vertical transistor architecture of claim 1, further comprising a storage capacitor electrically connected to a source/drain connection region of each selection transistor, whereby an array of memory cells each containing a vertical selection transistor is formed.

16. The vertical transistor architecture of claim 15, wherein the selection transistors are connected to the assigned storage capacitor in each case at an upper source/drain connection region.

17. A vertical transistor architecture comprising:

an array of vertical transistor cells formed in a substrate and arranged in a transistor plane, in rows in an x direction, and in columns in a y direction perpendicular to the x direction;

an array of active trenches, wherein the active trenches separate the rows of transistor cells; and

an array of isolation Wenches, wherein the isolation trenches separate the columns of transistor cells;

wherein active regions at least of transistor cells which are adjacent to one another in the x direction are connected to one another, whereby a charge carrier transport is made possible between the active regions of transistor cells which are adjacent in the x direction;

wherein the vertical transistor cells comprise;

respective lower source/drain connection region;

respective upper source/drain connection regions arranged above the lower source drain regions;

respective conductive channels disposed between the upper and lower source/drain connection regions; and

respective gate electrodes insulated from the active regions by a gate dielectric;

wherein the active regions are in each case sections of a contiguous layer body, wherein the contiguous body is patterned at least by the isolation trenches in an upper region, and wherein the contiguous body in a lower region connects the active regions of transistor cells that are adjacent to one another at least in the x direction; and

wherein a connection plate is patterned in an upper region by the active trenches extending along the x axis, wherein the lower source/drain connection regions are formed in the upper region of the connection plate in each case below the active regions, wherein the isolation trenches have a smaller depth than the active trenches, and wherein the layer bodies are formed contiguously row by raw in each in a lower region below the isolation trenches.

18. The vertical transistor architecture of claim 17, wherein the isolation trenches are filled with an insulator material.

19. A vertical transistor architecture comprising:

an array of vertical transistor cells formed in a substrate and arranged in a transistor plane, in rows in an x direction, and in columns in a y direction perpendicular to the x direction;

an array of active trenches, wherein the active trenches separate the rows of transistor cells; and

an array of isolation trenches, wherein the isolation trenches separate the columns of transistor cells;

wherein active regions at least of transistor cells which are adjacent to one another in the x direction are connected to one another, whereby a charge carrier transport is made possible between the active regions of transistor cells which are adjacent in the x direction;

wherein the vertical transistor cells comprise;

respective lower source/drain connection region;

respective upper source/drain connection regions arranged above the lower source drain regions;

respective conductive channels disposed between the upper and lower source/drain connection regions; and

respective gate electrodes insulated from the active regions by a gate dielectric;

wherein the active regions are in each case sections of a contiguous layer body, wherein the contiguous body is patterned at least by the isolation trenches in an upper region, and wherein the contiguous body in a lower region connects the active regions of transistor cells that are adjacent to one another at least in the x direction; and

wherein an upper region of a connection plate is patterned in the x direction and in the y direction, wherein a lower source/drain connection region delimited in the x direction and the y direction is in each case formed in the upper region of the connection plate, and wherein the active regions of transistor cells which are adjacent in the x direction and the y direction are formed contiguously by a single layer body which is patterned by the lower source/drain connection regions.

20. The vertical transistor architecture of claim 19, wherein the layer body is connected to a structure having a substrate potential.