Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration

• US 7,109,547 B2
• Filed: 12/19/2005
• Issued: 09/19/2006
• Est. Priority Date: 08/11/2000
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Arai, Fumitaka, Shimizu, Kazuhiro
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US11/305,216
• Publication Number:
  US 20060097309A1
• Time in Patent Office: 274 Days
• Field of Search: 257/314
• US Class Current: 257/314
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

First and second semiconductor regions are formed apart from each other on a semiconductor body. A stacked gate is formed on the semiconductor body between the first and second semiconductor regions. The stacked gate has a first side surface, a second side surface opposed to the first side surface, and an upper surface. A contact material is buried in an interlayer insulating film above the semiconductor body, to be adjacent to the first side surface of the stacked gate. The contact material contacts the first semiconductor region. A first insulating film is formed on the second side surface and the upper surface, except the first side surface of the stacked gate adjacent to the contact material. A second insulating film is formed on the first side surface of the stacked gate adjacent to the contact material, and the first insulating film.

Claims

1. A non-volatile semiconductor memory device, comprising:

a semiconductor substrate including a memory cell region and a peripheral region, the memory cell region including a plurality of first element regions and a plurality of first element separate regions which insulate between the first element regions, each first element separate region extending toward a first direction, the peripheral region including a second element region and a second element separate region which insulates the second element region;

a plurality of control gates, each control gate being formed over the first element region and the first element separate region and extending toward a second direction crossing to the first direction;

a plurality of charge storage portions, each charge storage portion being formed between the control gate and the first element region;

a first insulating film formed between the semiconductor substrate and the charge storage portions;

a second insulating film formed between the charge storage portions and the control gates;

a third insulating film formed on the second element region; and

a peripheral gate formed on the third insulating film, the peripheral gate including a first electrode portion, a second electrode portion and a fourth insulating film located between the first and the second electrode portions;

wherein

a first upper surface of the first element separate regions facing to the control gate protrudes from a second upper surface of the semiconductor substrate, a height of the first upper surface is lower than a height of a third upper surface of the charge storage portion, a fourth upper surface of the first element separate regions between the control gates is lower than the height of the first upper surface, and a fifth upper surface of the second element separate region protrudes from the second upper surface and is lower than a height of the fourth insulating film relative to the second upper surface.

2. The non-volatile semiconductor memory device according to claim 1, wherein the fourth upper surface protrudes from the second upper surface.

3. The non-volatile semiconductor memory device according to claim 1, wherein each charge storage portion includes a first portion located between the first element separate portions and a second portion has a sixth upper surface which is higher than the first upper surface.

4. The non-volatile semiconductor memory device according to claim 3, wherein the second portion of the charge storage portion extends on the first upper surface.

5. The non-volatile semiconductor memory device according to claim 1, further comprising a bit line formed over the control gate, the bit line extending toward the first direction.

6. The non-volatile semiconductor memory device according to claim 5, further comprising a contact connecting between the bit line and the charge storage portion, the contact being located between the control gates and on the first element region.

7. The non-volatile semiconductor memory device according to claim 1, further comprising a gate barrier film covering the control gate and the charge storage portion.

8. The non-volatile semiconductor memory device according to claim 7, further comprising a contact barrier film covering the gate barrier film.

9. The non-volatile semiconductor memory device according to claim 7, wherein the gate barrier film covers the peripheral gate.

10. The non-volatile semiconductor memory device according to claim 8, wherein the contact barrier film covers the gate barrier film of the peripheral gate.

11. The non-volatile semiconductor memory device according to claim 1, wherein a thickness of the third insulating film is thicker than a thickness of the first insulating film.