Apparatus and method for PCB smoke and burn detection and prevention

• US 7,109,722 B2
• Filed: 06/10/2004
• Issued: 09/19/2006
• Est. Priority Date: 06/10/2004
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Singh, Prabjit, Trifilo, Timothy M., Chamberlin, Bruce J.
• Primary Examiner(s): Nguyen, Vincent Q.
• Application Number:
  US10/865,598
• Publication Number:
  US 20050275552A1
• Time in Patent Office: 831 Days
• Field of Search: 324/551
• US Class Current: 324/551
• CPC Class Codes: H05K 1/0256 Electrical insulation details, e.g. around high voltage areas
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/0761 Insulation resistance, e.g. of the surface of the PCB between the conductors
• CPC Class Codes: H05K 2201/09781 Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2203/163 Monitoring a manufacturing process

Abstract

An apparatus and method for at least one of detecting and preventing burning of a PCB is disclosed. The method includes configuring a first comb array defined by a plurality of first fingers at a first potential; configuring a second comb array defined by a plurality of second fingers at a second potential different from the first potential; interlacing the plurality of first fingers defining the first comb array with the plurality of second fingers defining the second comb array embedded in a substrate; disposing the substrate with the PCB; and detecting a rise in leakage current between the first and second comb arrays indicative of a breakdown of the substrate.

Claims

1. A method for at least one of detecting and preventing burning of a PCB, the method comprising:

configuring a first comb array defined by a plurality of first fingers at a first potential;

configuring a second comb array defined by a plurality of second fingers at a second potential different from said first potential;

interlacing said plurality of first fingers defining said first comb array with said plurality of second fingers defining said second comb array embedded in a substrate;

disposing said substrate with the PCB; and

detecting a rise in leakage current between said first and second comb arrays indicative of a breakdown of said substrate,

wherein said interlacing of said first and second comb arrays is coplanar and includes a layer of epoxy and fiberglass above and below a sensing element defined by said first and second comb arrays arranged in a sensing plane.

2. The method of claim 1 wherein:

said substrate is an epoxy.

3. The method of claim 1 wherein:

said sensing element is disposed relative to said sensing plane in a manner to maximize monitoring as much of an area defining the PCB as is possible.

4. The method of claim 1 wherein:

said sensing element is disposed relative to an area defining said sensing plane only in areas where the PCB has some probability of deterioration due to high imposed electric fields.

5. The method of claim 1 wherein:

said sensing plane is disposed under a top signal layer of the PCB.

6. The method of claim 1 wherein:

said first and second comb arrays are each defined by a plurality of first and second branch traces, respectively, contiguous first branch traces having one second branch trace therebetween and contiguous second branch traces having one first branch trace therebetween.

7. The method of claim 6 wherein:

spacing between contiguous first and second branch traces is greater than about 0.003 inch.

8. A method for at least one of detecting and preventing burning of a PCB, the method comprising:

configuring a first comb array defined by a plurality of first fingers at a first potential;

configuring a second comb array defined by a plurality of second fingers at a second potential different from said first potential;

interlacing said plurality of first fingers defining said first comb array with said plurality of second fingers defining said second comb array embedded in a substrate;

disposing said substrate with the PCB; and

detecting a rise in leakage current between said first and second comb arrays indicative of a breakdown of said substrate,

wherein contiguous pairs of each interlaced first and second fingers have one of a BGA and a LGA conductive pad therebetween, each column of said one of the BGA and the LGA pads includes two separate branch traces at different potentials, each branch trace including a plurality of one of said first and second fingers extending therefrom.

9. An apparatus for at least one of detecting and preventing burning of a PCB comprising:

a first comb array defined by a plurality of first fingers at a first potential;

a second comb array defined by a plurality of second fingers at a second potential different from said first potential, said plurality of first fingers defining said first comb array interlaced with said plurality of second fingers defining said second comb array embedded in a substrate;

a PCB disposed with said substrate to detect a rise in leakage current between said first and second comb arrays indicative of a breakdown of said substrate,

wherein said first comb array is interlaced with said second comb array is coplanar and includes a layer of epoxy and fiberglass above and below a sensing element defined by said first and second comb arrays arranged in a sensing plane.

10. The apparatus of claim 9 wherein:

said substrate is an epoxy.

11. The apparatus of claim 9 wherein:

said sensing element is disposed relative to said sensing plane in a manner to maximize monitoring as much of an area defining the PCB as is possible.

12. The apparatus of claim 9 wherein:

said sensing element is disposed relative to an area defining said sensing plane only in areas where the PCB has some probability of deterioration due to high imposed electric fields.

13. The apparatus of claim 9 wherein:

said sensing plane is disposed under a top signal layer of the PCB.

14. The apparatus of claim 9 wherein:

said first and second comb arrays are each defined by a plurality of first and second branch traces, respectively, contiguous first branch traces having one second branch trace therebetween and contiguous second branch traces having one first branch trace therebetween.

15. The apparatus of claim 14 wherein:

spacing between contiguous first and second branch traces is greater than about 0.003 inch.

16. The apparatus of claim 9 wherein:

contiguous pairs of each interlaced first and second fingers have one of a BGA and a LGA conductive pad therebetween.

17. The apparatus of claim 16 wherein:

each column of said one of a BGA and a LGA pads includes two separate branch traces at different potentials, each branch trace including a plurality of one of said first and second fingers extending therefrom.