Non-contact tester for electronic circuits

• US 7,109,730 B2
• Filed: 04/25/2005
• Issued: 09/19/2006
• Est. Priority Date: 09/19/2002
• Status: Expired due to Fees

• Current Assignee: Scanimetrics, Inc.
• Original Assignee: Scanimetrics, Inc.
• Inventors: Slupsky, Steven Harold
• Primary Examiner(s): Hollington, Jermele
• Assistant Examiner(s): Nguyen, Jimmy
• Application Number:
  US11/113,806
• Publication Number:
  US 20060066326A1
• Time in Patent Office: 512 Days
• Field of Search: None
• US Class Current: 324/754.21
• CPC Class Codes: G01R 31/2822 of microwave or radiofrequency circuits of attenuation, gain, e.g. using network analyzers G01R27/28
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/303 of integrated circuits G01R31/305 - G01R31/315 take precedence
• CPC Class Codes: G01R 31/315 by inductive methods

Abstract

A non-contact tester for electronic circuits consists of an electronic circuit and independent scanning head, in combination. The electronic circuit includes a micro-fabricated wireless i/o cell and means for sending and receiving signals via the wireless i/o cell. The independent scanning head has a wireless i/o cell that is compatible with the wireless i/o cell on the electronic circuit. This enables data to be exchanged with the electronic circuit to confirm proper functioning of the electronic circuit.

Claims

1. A tester for electronic circuits, comprising in combination:

an electronic circuit which includes a plurality of wireless i/o cells and means for sending and receiving signals via each of the wireless i/o cells, a wireless i/o cell being provided for each contact point on the electronic circuit to be tested;

an independent scanning head having a plurality of wireless i/o cells compatible with the wireless i/o cells on the electronic circuit, such that data may be exchanged with the electronic circuit to confirm proper functioning of the electronic circuit, the number of wireless i/o cells on the independent scanning head corresponding in a one to one relationship with the number of wireless i/o cells on the electronic circuit being tested;

the scanning head having a contact probe for power input to energize the electronic circuit.

2. The tester for electronic circuits as defined in claim 1, wherein each of the wireless i/o cells of the electronic circuit to be tested has an input pipeline and an output pipeline for each data signal.

3. The tester for electronic circuits as defined in claim 2, wherein a final element of each input pipeline is clocked a clock tree driven by a last element of clock tree and a final element of each output pipeline is clocked by the clock tree driven by a second last element of the clock tree.

4. The tester for electronic circuits as defined in claim 2, wherein delay locked loops are used to distribute a clock signal to both the input pipeline and the output pipeline.

5. The tester for electronic circuits as defined in claim 1, wherein yield enhancement is achieved through redundant transceiver circuits.

6. The tester for electronic circuits as defined in claim 1, wherein dual band transceivers are used with single channel, single carrier signal transmissions.