Integrated circuit output driver circuitry with programmable preemphasis

• US 7,109,743 B2
• Filed: 06/07/2005
• Issued: 09/19/2006
• Est. Priority Date: 01/07/2003
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wong, Wilson, Shumarayev, Sergey Y, Patel, Rakesh H, White, Thomas H
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/148,046
• Publication Number:
  US 20050237082A1
• Time in Patent Office: 469 Days
• Field of Search: 326/83, 326/21, 326/26, 326/29, 327/65, 327/66, 327/108
• US Class Current: 326/26
• CPC Class Codes: H03K 19/018585 programmable
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0286 Provision of wave shaping within the driver wave shaping per se H04L25/03834

Abstract

Programmable logic device integrated circuitry having differential I/O circuitry is provided. The differential I/O circuitry may include output drivers for providing differential digital output data signals across pairs of output lines. A user may program the I/O circuitry to accommodate different high-speed differential I/O signaling standards. The user may also program the I/O circuitry to provide a desired amount of preemphasis to the output data signals.

Claims

1. A programmable logic device, comprising:

differential circuitry that produces differential digital output data signals; and

preemphasis driver circuitry that produces preemphasis signals for steepening slopes of data bit edges in the differential digital output data signals, wherein the preemphasis driver circuitry includes programmable circuitry that is programmable with a plurality of slope parameter values to adjust an amount of slope steepening provided by the preemphasis driver circuitry.

2. The programmable logic device defined in claim 1, wherein the preemphasis driver circuitry comprises programmable current supply circuitry.

3. The programmable logic device defined in claim 1, wherein the preemphasis driver circuitry is programmable to adjust an amplitude of the preemphasis signals.

4. The programmable logic device defined in claim 1, wherein the preemphasis driver circuitry comprises:

programmable delay circuitry; and

pulse generation circuitry responsive to the signals.

5. The programmable logic device defined in claim 4, wherein shaping the preemphasis signals comprises adjusting a width of the preemphasis signals.

6. The programmable logic device defined in claim 1, wherein the preemphasis signals steepen slopes of leading and trailing edges of the differential digital output data signals.

7. The programmable logic device defined in claim 1, wherein the preemphasis signals are superimposed over the differential digital output data signals.

8. The programmable logic device defined in claim 1, further comprising a programmable function control element coupled to the programmable circuitry for storing the slope parameter.

9. A programmable logic device, comprising:

differential driver circuitry that produces differential digital output data signals, wherein the differential driver circuitry programmably accommodates different differential signaling standards; and

preemphasis driver circuitry that produces preemphasis signals for steepening slopes of data bit edges in the differential digital output data signals, wherein the preemphasis driver circuitry includes programmable circuitry that is programmable with a plurality of slope parameter values to adjust an amount of slope steepening provided by the preemphasis driver circuitry.

10. The programmable logic device defined in claim 9, wherein the preemphasis driver circuitry comprises programmable current supply circuitry.

11. The programmable logic device defined in claim 9, wherein the preemphasis driver circuitry is programmable to adjust an amplitude of the preemphasis signals.

12. The programmable logic device defined in claim 9, wherein the preemphasis driver circuitry comprises:

programmable delay circuitry; and

pulse generation circuitry responsive to the programmable delay circuitry for shaping the preemphasis signals.

13. The programmable logic device defined in claim 12, wherein shaping the preemphasis signals comprises adjusting a width of the preemphasis signals.

14. The programmable logic device defined in claim 9, wherein the preemphasis signals steepen slopes of leading and trailing edges of the differential digital output data signals.

15. The programmable logic device defined in claim 9, wherein the different differential signaling standards include at least one signaling standard selected from a group of standards consisting of LVPECL, LVDS, and PCML.

16. The programmable logic device defined in claim 9, wherein the preemphasis signals are superimposed over the differential digital output data signals.

17. The programmable logic device defined in claim 9, further comprising a programmable function control element coupled to the programmable circuitry for storing the slope parameter.

18. A programmable logic device, comprising:

differential driver circuitry that produces differential digital differential driver circuitry programmably accommodates output data signals, wherein the different differential signaling standards; and

programmable preemphasis driver circuitry that produces preemphasis signals that are superimposed over the differential digital output data signals, wherein the programmable preemphasis driver circuitry is programmable with a plurality of slope parameter values to steepen slopes of leading and trailing data bit edges in the differential digital output data signals.

19. The programmable logic device defined in claim 18, wherein the programmable preemphasis driver circuitry comprises programmable current supply circuitry.

20. The programmable logic device defined in claim 18, wherein the programmable preemphasis driver circuitry is programmable to adjust an amplitude of the preemphasis signals.

21. The programmable logic device defined in claim 18, wherein the programmable preemphasis driver circuitry comprises:

programmable delay circuitry; and

pulse generation circuitry responsive to the programmable delay circuitry for shaping the preemphasis signals.

22. The programmable logic device defined in claim 21, wherein shaping the preemphasis signals comprises adjusting a width of the preemphasis signals.

23. The programmable logic device defined in claim 18, wherein the different differential signaling standards include at least one signaling standard selected from a group of standards consisting of LVPECL, LVDS, and PCML.

24. The programmable logic device defined in claim 18, further comprising a programmable function control element coupled to the programmable preemphasis driver circuitry for storing the slope parameter.