Leakage-tolerant dynamic wide-NOR circuit structure

• US 7,109,757 B2
• Filed: 11/15/2004
• Issued: 09/19/2006
• Est. Priority Date: 11/15/2004
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lai, Peter F., Xiong, Ye, Yuan, Xeujun
• Primary Examiner(s): CHANG, DANIEL D
• Application Number:
  US10/990,140
• Publication Number:
  US 20060103430A1
• Time in Patent Office: 673 Days
• Field of Search: 326/95, 326/98, 326/112, 326/119, 326/121, 326/122, 365/203
• US Class Current: 326/95
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a precharge phase. The circuit also contains a plurality of parallel pull-down transistors which are coupled to the dynamic node. The pull-down transistors conditionally discharge the dynamic node during the evaluate phase. The keeper sustains a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors. In addition, the circuit contains a feedback gating device which is coupled between the keeper and the dynamic node. During the evaluation phase, the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.

Claims

1. A circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure, comprising:

a precharge device which is coupled to the dynamic node, wherein the precharge device precharges the dynamic node during a precharge phase;

a plurality of parallel pull-down transistors which are coupled to the dynamic node, wherein the pull-down transistors conditionally discharge the dynamic node during the evaluate phase;

the keeper, which is configured to sustain a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors; and

a feedback gating device which is coupled between the keeper and the dynamic node;

a narrow pulse generator which generates a feedback control signal that controls the feedback gating device, wherein the feedback control signal is active for a predetermined time which is shorter than the active phase of an input to the narrow pulse generator; and

wherein during the evaluation phase the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.

2. The circuit of claim 1, wherein at the beginning of the evaluate phase the feedback gating device is disabled by the feedback control signal for a predetermined time interval.

3. The circuit of claim 2, wherein the pre-determined time interval is long enough to allow the parallel pull-down transistors to conditionally discharge the dynamic node, but short enough to prevent the leakage current from causing a false evaluation of the dynamic node.

4. The circuit of claim 1, wherein the feedback gating device comprising

a PMOS transistor;

a switch;

or

a device which prevents the keeper from sustaining the precharged value on the dynamic node.

5. The circuit of claim 1, wherein the keeper is comprised of a feed-forward inverter coupled with a feedback PMOS device.

6. The circuit of claim 1, wherein the keeper is comprised of a feed-forward sense-amp coupled with a feedback PMOS device.

7. The circuit of claim 1, wherein the circuit with the dynamic wide-NOR structure is part of:

a memory array;

or a wide domino-NOR gate.

8. A method for blocking a keeper from interfering with a dynamic node during an evaluate phase for a dynamic wide-NOR structure, comprising:

when a feedback gating device is activated, causing the keeper to sustain a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through a group of inactive pull-down transistors during the evaluate phase;

precharging the dynamic node during a precharge phase; and

upon leaving the precharge phase and entering the evaluate phase,

using a narrow pulse generator to generate a feedback control signal for the feedback gating device, wherein the feedback control signal is active for a predetermined time which is shorter than the active phase of an input to the narrow pulse generator;

deactivating the feedback gating device, thereby preventing the keeper from sustaining the precharged value on the dynamic node, and

conditionally discharging the dynamic node without interference from the keeper.

9. The method of claim 8, wherein at the beginning of the evaluate phase the feedback gating device is disabled by the feedback control signal for a pre-determined time interval.

10. The method of claim 9, wherein the pre-determined time interval is long enough to allow the parallel pull-down transistors to conditionally discharge the dynamic node, but short enough to prevent the leakage current from causing a false evaluation of the dynamic node.

11. The method of claim 8, wherein the feedback gating device comprising:

a PMOS transistor;

a switch;

or

a device which prevents the keeper from sustaining the precharged value on the dynamic node.

12. The method of claim 8, wherein the keeper is comprised of a feed-forward inverter coupled with a feedback PMOS device.

13. The method of claim 8, wherein the keeper is comprised of a feed-forward sense-amp coupled with a feedback PMOS device.

14. The method of claim 8, wherein the circuit with the dynamic wide-NOR structure is part of:

a memory array;

or

a wide domino-NOR gate.

15. A computer system, comprising:

a processor;

a memory;

a dynamic wide-NOR structure which blocks a keeper from interfering with a dynamic node during an evaluation phase;

a precharge device which is coupled to the dynamic node, wherein the precharge device precharges the dynamic node during a precharge phase;

the keeper, which is configured to sustain a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors;

a plurality of parallel pull-down transistors which are coupled to the dynamic node, wherein the pull-down transistors conditionally discharge the dynamic node during the evaluate phase; and

a feedback gating device which is coupled between the keeper and the dynamic node;

a narrow pulse generator which generates a feedback control signal that controls the feedback gating device, wherein the feedback control signal is active for a predetermined time which is shorter than the active phase of an input to the narrow pulse generator; and

wherein during the evaluation phase the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.

16. The computer system of claim 15, wherein at the beginning of the evaluate phase the feedback gating device is disabled by the feedback control signal for a pre-determined time interval.

17. The computer system of claim 16, wherein the pre-determined time interval is long enough to allow the parallel pull-down transistors to conditionally discharge the dynamic node, but short enough to prevent the leakage current from causing a false evaluation of the dynamic node.

18. The computer system of claim 15, wherein the feedback gating device comprising:

a PMOS transistor;

a switch;

or

a device which prevents the keeper from sustaining the precharged value on the dynamic node.

19. The computer system of claim 15, wherein the keeper is comprised of a feed-forward inverter coupled with a feedback PMOS device.

20. The computer system of claim 15, wherein the keeper is comprised of a feed-forward sense-amp coupled with a feedback PMOS device.

21. The computer system of claim 15, wherein the dynamic wide-NOR structure is part of:

a memory array;

or

a wide domino-NOR gate.