Power management for spatial power combiners
First Claim
1. An integrated, spatial power-combining system, comprising:
- (a) a spatial power-combining chip having(i) a front surface with a plurality of active devices disposed thereon, and(ii) a back surface with patterned, electrically-conductive material disposed thereon; and
(b) a thermally-conductive, dielectric substrate having a front surface attached to the back surface of the spatial power-combining chip.
3 Assignments
0 Petitions
Accused Products
Abstract
The present invention discloses a system for improving power management for spatial power combining systems, such as a quasi optical grid array amplifier. One aspect of the invention includes the provision of a patterned conductor on the surface the semiconductor chip that opposes the surface upon which the active devices are disposed. This metal material can be used to both enhance heat removal from the chip and to provide a new and more efficient DC biasing path (with the use of vias) for the active components on the other (front) surface of the chip. Another aspect of the invention is the introduction of a dielectric superstrate that attaches to the front surface of the chip to provide an alternative or complementary heat removal and/or biasing structure to the conventional substrate that is typically attached to the back side of the chip. Various combinations of the above features are disclosed.
29 Citations
22 Claims
-
1. An integrated, spatial power-combining system, comprising:
-
(a) a spatial power-combining chip having (i) a front surface with a plurality of active devices disposed thereon, and (ii) a back surface with patterned, electrically-conductive material disposed thereon; and (b) a thermally-conductive, dielectric substrate having a front surface attached to the back surface of the spatial power-combining chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. An integrated spatial power-combining system, comprising:
-
(a) a spatial power-combining chip having front and back surfaces and active devices integrated on the front surface; and (b) a thermally-conductive, dielectric superstrate having a back surface attached to the front surface of the spatial power-combining chip, wherein the back surface of the dielectric superstrate includes patterned, electrically-conductive material disposed thereon that is connected to the front surface of the power-combining chip. - View Dependent Claims (12, 13, 14, 15)
-
-
16. A method of drawing heat away from a spatial power-combining chip having a front surface with heat-generating, active components disposed thereon and a back surface that is connected to a thermally-conducting substrate, comprising:
-
(a) providing a metal pattern on the back surface of the chip; (b) providing a metal pattern on the front surface of the substrate; and (c) joining the metal pattern on the back surface of the chip to the metal pattern on the front surface of the substrate in order to draw heat generated by the active devices away from the chip.
-
-
17. A method of drawing heat away from a spatial power-combining chip having a front surface with a plurality of heat-generating active devices disposed thereon, comprising:
-
(a) providing a thermally-conducting dielectric superstrate having front and back surfaces; and (b) attaching the front surface of the power-combining chip to the back surface of the superstrate via a thermally-conducting joint. - View Dependent Claims (18, 19)
-
-
20. A method of providing DC power to active components on a power-combining chip having front and back surfaces, wherein the components are disposed on the front surface of the chip, comprising:
-
(a) providing a metal pattern on the back surface of the power-combining chip; (b) selectively connecting one or more of the active components to the metal pattern on the back surface of the chip; (c) providing DC power to the metal pattern on the back surface of the chip; (d) providing a thermally-conducting, dielectric substrate having a front surface with a metal pattern disposed thereon; (e) electrically connecting the metal pattern on the front surface of the dielectric substrate to the metal pattern on the back surface of the power-combining chip; and (f) supplying DC power to the metal pattern on the front surface of the dielectric substrate. - View Dependent Claims (21)
-
-
22. A method of providing DC power to active components on a power-combining chip having front and back surfaces, wherein the components are disposed on the front surface of the chip, comprising:
-
(a) providing a thermally-conducting dielectric superstrate having a back surface with a metal pattern disposed thereon; (b) electrically connecting the metal pattern on the back surface of the superstrate to selected components on the front surface of the chip; and (c) applying DC power to the metal pattern on the back surface of the superstrate.
-
Specification