Universial energy conditioning interposer with circuit architecture

• US 7,110,227 B2
• Filed: 09/09/2002
• Issued: 09/19/2006
• Est. Priority Date: 04/08/1997
• Status: Expired due to Fees

• Current Assignee: X2Y Attenuators, LLC
• Original Assignee: X2Y Attenuators, LLC
• Inventors: Anthony, Anthony A., Anthony, William M.
• Primary Examiner(s): Jackson, Stephen W.
• Application Number:
  US10/237,079
• Publication Number:
  US 20030067730A1
• Time in Patent Office: 1,471 Days
• Field of Search: 361/15, 361/18, 361/58, 361/111, 361/113, 361/117, 361/118, 361/127, 361/120, 361/91.1
• US Class Current: 361/56
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01G 4/35 Feed-through capacitors or anti-noise capacitors
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/162 : incorporating printed capacitors
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 9/0039 : Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing printed shielding conductors, ground planes or power planes for reduction of cross-talk or noise in printed circuits H05K1/0218

Abstract

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Claims

1. An integral capacitor comprising:

a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency;

a first ground plane having a first ground surface and a first ground periphery, the first ground plane coupling ground to the signals, the first ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface;

the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance; and

a dielectric layer formed between the power plane and the first ground plane.

2. The integral capacitor of claim 1 further comprising:

a second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance;

the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery;

the fourth distance being at least larger than M times the third distance, the second ground plane being coupled to the first ground plane by a via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery; and

the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency.

3. The integral capacitor of claim 1 wherein the dielectric layer is made of a dielectric material having a high dielectric constant.

4. The integral capacitor of claim 1 wherein N is an integer ranging from 1 to 20.

5. The integral capacitor of claim 1 wherein M is an integer ranging from 1 to 20.

6. The integral capacitor of claim 1 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

7. The integral capacitor of claim 6 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

8. The integral capacitor of claim 1 further comprises a contact array to connect to at least the first ground plane and the power plane.

9. The integral capacitor of claim 8 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.

10. The integral capacitor of claim 9 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

11. A packaged device comprising:

a die containing an integrated circuit;

a plurality of controlled collapse chip connection (C4) bumps attaching the die to a substrate; and

an integral capacitor attaching to the die to reduce radiation, the integral capacitor comprising;

a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency, a first ground plane having a first ground surface and a first ground periphery, the first ground plane coupling ground to the signals, the first

ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface and the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance, and a dielectric layer formed between the power plane and the first ground plane.

12. The packaged device of claim 11 wherein the integral capacitor further comprising:

a second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance, the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery, the fourth distance being at least larger than M times the third distance, the second ground plane being coupled to the first ground plane by a via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency.

13. The packaged device of claim 12 wherein the dielectric layer is made of a dielectric material having a high dielectric constant.

14. The packaged device of claim 11 wherein N is an integer ranging from 1 to 20.

15. The packaged device of claim 11 wherein M is an integer ranging from 1 to 20.

16. The packaged device of claim 11 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

17. The packaged device of claim 16 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

18. The packaged device of claim 11 wherein the integral capacitor further comprises a contact array to connect to at least the first ground plane and the power plane.

19. The packaged device of claim 18 wherein the contact array is one of a C4) bump array, a BGA ball array, and a FCPGA pin array.

20. The packaged device of claim 19 wherein the ground plane has a plurality 15 of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter, wavelength of the fundamental frequency.

21. A method comprising:

coupling power to signals of an integrated circuit operating at a fundamental frequency by a power plane having a power surface and a power periphery;

coupling ground to the signals by a first ground plane having a first ground surface 5 and a first ground periphery, the first ground plane being separated from the power plane by a first distance, the first ground surface being larger than the power surface and the first ground periphery extending at least a second distance from the power periphery, the second distance being at least larger than N times the first distance; and

forming a dielectric layer between the power plane and the first ground plane.

22. The method of claim 21 further comprising:

coupling a second ground plane to the first ground plane by a via chain, the second ground plane having a second ground surface and a second ground periphery, the second ground plane being separated from the power plane by the third distance, the second ground surface being larger than the power surface and the second ground periphery extending at least a fourth distance from the power periphery, the fourth distance being at least larger than M times the third distance, the via chain connecting a first plurality of vias located around the first ground periphery to a second plurality of vias located around the second ground periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency.

23. The method of claim 22 wherein the dielectric layer is made of a dielectric material having a high dielectric constant.

24. A method of claim 21 wherein N is an integer ranging from 1 to 20.

25. The method of claim 21 wherein M is an integer ranging from 1 to 20.

26. The method of claim 21 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

27. The method of claim 26 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

28. The method of claim 21 further comprises connecting to at least the first ground plane and the power plane by a contact array.

29. The method of claim 28 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.

30. The method of claim 29 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

31. An energy conditioner comprising;

a first pathway having a first surface and a first perimeter, and the first pathway coupled to an integrated circuit;

a second pathway having a second surface and a second perimeter, and the second pathway coupled to the integrated circuit;

the second pathway being separated from the first pathway by a first distance;

the second surface being larger than the first surface;

the second perimeter extending at least a second distance from the first perimeter;

the second distance being at least larger than a number times the first distance; and

a dielectric layer formed between the first pathway and the second pathway.

32. An enclosure comprising:

a power plane having a power surface and a power periphery, the power plane coupling power to signals of an integrated circuit operating at a fundamental frequency; and

first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes coupling ground to the signals, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power peppery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively.

33. The enclosure of claim 32 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain.

34. The enclosure of claim 33 wherein the signals are on a signal plane located between the power plane and the second ground plane.

35. The enclosure of claim 32 wherein N is an integer ranging from 1 to 20.

36. The enclosure of claim 32 wherein M is an integer ranging from 1 to 20.

37. The enclosure of claim 32 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

38. The enclosure of claim 37 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

39. The enclosure of claim 32 further comprises a contact array to connect to at least the first ground plane and the power plane.

40. The enclosure of claim 39 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.

41. The enclosure of claim 40 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

42. A packaged device comprising:

a die containing an integrated circuit having signals operating at a fundamental frequency;

a plurality of controlled collapse chip connection (C4) bumps attaching the die to a substrate; and

an enclosure attaching to the die to reduce radiation, the enclosure comprising;

a power plane having a power surface and a power periphery, the power plane coupling power to the signals of the integrated circuit, and

first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes coupling ground to the signals, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power periphery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively.

43. The packaged device of claim 42 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain.

44. The packaged device of claim 43 wherein the signals are on a signal plane located between the power plane and the second ground plane.

45. The packaged device of claim 42 wherein N is an integer ranging from 1 to 20.

46. The packaged device of claim 42 wherein M is an integer ranging from 1 to 20.

47. The packaged device of claim 42 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

48. The packaged device of claim 47 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

49. The packaged device of claim 42 wherein the enclosure further comprises a contact array to connect to at least the first ground plane and the power plane.

50. The packaged device of claim 49 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.

51. The packaged device of claim 50 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

52. A method comprising:

coupling power to signals of an integrated circuit operating at a fundamental frequency by a power plane having a power surface and a power periphery; and

coupling pound to the signals by first and second ground planes having first and second ground surfaces and first and second ground peripheries, the first and second ground planes being separated from the power plane by first and second distances, respectively, the first and second ground surfaces being larger than the power surface, the first and second ground peripheries extending at least third and fourth distances from the power periphery, respectively, the third and fourth distances being N and M times larger than the first and second distances, respectively.

53. The method of claim 52 wherein the first and second ground planes have first and second pluralities of vias located around the first and second ground peripheries, respectively, and outside the power periphery, the first and second pluralities of vias having adjacent vias, the adjacent vias being spaced apart by a via distance that is smaller than a quarter wavelength of the fundamental frequency, the first and second pluralities of vias being connected by a via chain.

54. The method of claim 53 wherein the signals are on a signal plane located between the power plane and the second ground plane.

55. The method of claim 52 wherein N is an integer ranging from 1 to 20.

56. The method of claim 52 wherein M is an integer ranging from 1 to 20.

57. The method of claim 52 wherein the first plurality of vias having electrical contact to a plurality of adjacent contacts, the adjacent contacts being spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.

58. The method of claim 57 wherein the contacts are ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.

59. The method of claim 52 further comprises connecting to at least the first ground plane and the power plane by a contact array.

60. The method of claim 59 wherein the contact array is one of a C4 bump array, a BGA ball array, and a FCPGA pin array.

61. The method of claim 60 wherein the ground plane has a plurality of adjacent contacts, the adjacent contacts being ones of controlled collapse chip connection (C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins and spaced apart by a contact distance that is smaller than a quarter wavelength of the fundamental frequency.