Memory module including an integrated circuit device

• US 7,110,322 B2
• Filed: 09/14/2004
• Issued: 09/19/2006
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/939,501
• Publication Number:
  US 20050030802A1
• Time in Patent Office: 735 Days
• Field of Search: None
• US Class Current: 365/189.15
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module including an integrated circuit is disclosed. In one particular exemplary embodiment, the memory module may comprise a plurality of memory devices and an integrated circuit device that is coupled to the plurality of memory devices. The integrated circuit device includes a first circuit to receive control information specifying a write operation, and address information specifying a memory location corresponding to the write operation, wherein the memory location is in a first memory device of the plurality of memory devices, and wherein the control information and the address information are received in a multiplexed format. The integrated circuit device also includes a second circuit, including a plurality of output drivers, to output data after a first number of clock cycles of an external clock signal transpire, wherein the data is to be written to the first memory device during the write operation.

Claims

1. A memory module comprising:

a plurality of memory devices; and

an integrated circuit device, coupled to the plurality of memory devices, the integrated circuit device including;

a first circuit to receive;

control information specifying a write operation; and

address information specifying a memory location corresponding to the write operation, wherein the memory location is in a first memory device of the plurality of memory devices, and wherein the control information and the address information are received in a multiplexed format; and

a second circuit, including a plurality of output drivers, to output data after a first number of clock cycles of an external clock signal transpire, wherein the data is to be written to the first memory device during the write operation.

2. The memory module of claim 1, wherein:

the integrated circuit device receives control information specifying a read operation;

the integrated circuit device outputs an operation code corresponding to the read operation to the first memory device;

the first memory device outputs read data in response to the operation code; and

the integrated circuit device further comprises a plurality of input receivers to receive the read data after a second number of clock cycles of the external clock signal transpire.

3. The memory module of claim 1, wherein the plurality of output drivers of the second circuit includes output drivers to output a value to the first memory device, wherein the value is representative of the first number of clock cycles of the external clock signal, wherein the first memory device stores the value in a register.

4. The memory module of claim 1, wherein the integrated circuit device receives a value that is representative of the first number of clock cycles of the external clock signal, and wherein the plurality of output drivers of the second circuit includes output drivers to output the value to the first memory device, wherein the first memory device stores the value in a register.

5. The memory module of claim 1, wherein the plurality of output drivers of the second circuit includes output drivers to output, to the first memory device, a value that indicates an amount of the data output to the first memory device.

6. The memory module of claim 1, wherein the plurality of output drivers of the second circuit includes output drivers to output a value, to the first memory device, that is representative of a data transfer amount associated with a data transfer operation involving the first memory device.

7. The memory module of claim 1, wherein the plurality of output drivers of the second circuit includes at least one output driver to output information that represents a range of addresses to the first memory device, wherein the information uniquely identifies the first memory device from other memory devices of the plurality of memory devices.

8. The memory module of claim 1, wherein the plurality of output drivers of the second circuit includes at least one output driver to output a device identification value to the first memory device, wherein the device identification value uniquely identifies the first memory device from other memory devices of the plurality of memory devices.

9. The memory module of claim 1, wherein the integrated circuit device forwards the address information to the first memory device.

10. The memory module of claim 1, wherein the integrated circuit device forwards the control information to the first memory device.

11. The memory module of claim 1, further including a bus coupling the first memory device to the integrated circuit device, wherein the plurality of output drivers outputs, in a multiplexed format, the control information and the address information to the first memory device using the bus.

12. The memory module of claim 1, wherein the first circuit receives the control information and the address information in a packet format, and wherein the first circuit includes a receiver to receive a signal that indicates the beginning of a packet.

13. The memory module of claim 1, wherein the integrated circuit device stores a value that is representative of the number of clock cycles of the external clock signal.

14. The memory module of claim 1, wherein each output driver of the plurality of output drivers outputs two bits of the data during a single clock cycle of the external clock signal.

15. The memory module of claim 1, wherein the integrated circuit device further includes a third circuit to generate a first internal clock signal, wherein the third circuit includes a feedback loop to control the timing relationship of the first internal clock signal with respect to the external clock signal, wherein the plurality of output drivers outputs the data using the internal clock signal.

16. The memory module of claim 15, wherein the third circuit further generates a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein the plurality of output drivers further outputs a first portion of the data using the first internal clock signal and the plurality of output drivers outputs a second portion of the data, in succession to the first portion of the data, using the second internal clock signal.

17. The memory module of claim 16, wherein the integrated circuit device receives the external clock signal and a delayed version of the external clock signal, wherein:

transition of the first internal clock signal occurs between a rising edge transition of the clock signal and a rising edge transition of the delayed version of the external clock signal; and

the second internal clock signal is generated such that a transition of the second internal clock signal occurs between a falling edge transition of the external clock signal and a falling edge transition of the delayed version of the external clock signal.

18. The memory module of claim 17, further including:

a first clock line coupled to the integrated circuit device, wherein the integrated circuit device receives the external clock signal from the first clock line; and

a second clock line coupled to the integrated circuit device, wherein the integrated circuit device receives the delayed version of the external clock signal from the second clock line.

19. The memory module of claim 18, wherein the first clock line is coupled to the second clock line, and wherein the first memory device is coupled to the first clock line to receive the external clock signal, and the first memory device is coupled to the second clock line to receive the delayed version of the external clock signal.

20. The memory module of claim 1, wherein output drivers, of the plurality of output drivers provide to the first memory device, control information includes information specifying whether the first memory device is to precharge a plurality of sense amplifiers after performing the write operation, wherein the sense amplifiers are used to write the data to the memory array during the write operation.

21. A method of operation in a memory module that includes a plurality of memory devices and an integrated circuit device, the method comprising:

receiving at pins of the integrated circuit device, in a multiplexed format, control information and address information, the control information specifying a write operation, and the address information specifying a location within a memory array for the write operation, wherein the memory array is located on a first memory device of the plurality of memory devices;

outputting to the memory device, an operation code that corresponds to the write operation; and

receiving at pins of the first memory device, data to be written to the memory array during the write operation, after a predetermined number of clock cycles of an external clock signal transpire, wherein the data is received in response to the operation code.

22. The method of claim 21, further including:

receiving at pins of the integrated circuit device, control information specifying a read operation;

outputting an operation code that corresponds to the control information to the first memory device, wherein the first memory device outputs read data in response to the operation code; and

sampling the read data, output by the first memory device, after a delay time transpires, wherein the sampling is done by input receivers on the integrated circuit device such that each input receiver samples two bits of the read data during a single clock cycle of the external clock signal.

23. The method of claim 21, further including outputting a value to the first memory device, wherein the value is representative of the predetermined number of clock cycles of the external clock signal.

24. The method of claim 21, further including:

receiving a value that is representative of the predetermined number of clock cycles of the external clock signal; and

outputting the value to the first memory device.

25. The method of claim 21, further including outputting to the first memory device, a value that indicates an amount of the data that the first memory device receives from the integrated circuit device.

26. The method of claim 21, further including outputting the data by output drivers on the integrated circuit device such that each output driver outputs two bits of the data for during a single clock cycle of the external clock signal.

27. The method of claim 21, further including forwarding the address information to the first memory device.

28. The method of claim 21, further including forwarding the control information to the first memory device.

29. The method of claim 21, further including:

generating a first internal clock signal using the external clock signal; and

controlling a timing relationship between the first internal clock signal and the external clock signal using a feedback loop;

wherein outputting data includes outputting data using the first internal clock signal.

30. The method of claim 29, further including generating a second internal clock signal, wherein the first and second internal clock signals are complementary, and wherein outputting data includes outputting the data using the second internal clock signal.

31. A memory module comprising:

a plurality of memory devices including a first memory device; and

an integrated circuit device, coupled to the plurality of memory devices, the integrated circuit device including;

means for receiving control information and address information in a multiplexed format, the control information specifying a write operation, and the address information specifying a memory location in the first memory device for the write operation;

means for outputting an operation code, corresponding to the write operation, to the memory device; and

means for outputting data after a predetermined number of clock cycles of an external clock signal transpire from outputting the operation code, wherein the data is to be written to the memory array during the write operation.