Random number generating circuit

• US 7,111,029 B2
• Filed: 09/06/2002
• Issued: 09/19/2006
• Est. Priority Date: 09/26/2001
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohba, Ryuji, Uchida, Ken, Fujita, Shinobu, Koga, Junji
• Primary Examiner(s): Ngo, Chuong D.
• Application Number:
  US10/235,827
• Publication Number:
  US 20030061250A1
• Time in Patent Office: 1,474 Days
• Field of Search: 708/250, 708/251, 708/255
• US Class Current: 708/250
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/0861 Generation of secret information including derivation or calculation of cryptographic keys or passwords

Abstract

A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of “0” and “1” in the digital output values output from the uncertain logic circuit.

Claims

1. A random number generating circuit comprising:

an uncertain logic circuit including a flip-flop logic circuit which provides digital output values not definitely determined by a digital input value; and

an equalizing circuit which equalizes appearance frequencies of “

0” and

“

1”

in said digital output values from said uncertain logic circuit;

wherein said uncertain logic circuit includes at least four NOR circuits or NAND circuits that are in chain connection with output of each of said NOR or NAND circuits being connected to one of inputs of next NOR or NAND circuit.

2. A random number generating circuit according to claim 1, wherein said equalizing circuit includes a circuit for operating exclusive OR by using said digital output value from said uncertain logic circuit.

3. A random number generating circuit according to claim 2, wherein said flip-flop logic circuit is an RS flip-flop, and wherein said uncertain logic circuit alternately introduce a combination of input data for obtaining the value maintaining the preceding state and a combination of input data causing invalidation of the flip-flop to continuously make the output from said RS flip-flop uncertain.

4. A random number generating circuit according to claim 2, wherein said equalizing circuit operates exclusive OR of a plurality of digital signals output from said uncertain logic circuit, and outputs it as random numbers.

5. A random number generating circuit according to claim 2, wherein said equalizing circuit operates exclusive OR of a digital signal sequence containing “

0” and

“

1”

by 1;

1 in appearance digital signal sequence output from said uncertain logic circuit, and outputs it as a digital random number sequence.

6. A random number generating circuit according to claim 1, wherein the number of said at least four NOR or NAND circuits is an even number.

7. A random number generating circuit according to claim 6, wherein uncertain outputs obtained by alternately introducing “

1” and

“

0”

to individual inputs of said NOR circuits or NAND circuits to form said digital output values are not determined definitely.

8. A random number generating circuit according to claim 7, wherein outputs from even-numbered or odd-numbered ones of said NOR circuits or NAND circuits are employed as said digital output values.

9. A random number generating circuit according to claim 6, wherein said digital output values not determined definitely are created by using uncertain outputs which are obtained by first introducing arbitrary data to inputs of said NOR circuits in chain connection and subsequently introducing “

0”

to all said inputs.

10. A random number generating circuit according to claim 9, wherein said arbitrary data is created by digitizing outputs from a plurality of asynchronous oscillator circuits.

11. A random number generating circuit according to claim 10, wherein said asynchronous oscillator circuits are different in oscillating frequency from each other.

12. A random number generating circuit according to claim 9, wherein said arbitrary data is obtained by combining outputs from arbitrary shift registers forming a feedback shift register.

13. A random number generating circuit according to claim 6, wherein said digital output values not determined definitely are created by using uncertain outputs which are obtained by first introducing arbitrary data to inputs of said NAND circuits in chain connection and subsequently introducing “

1”

to all said inputs.

14. A random number generating circuit comprising:

an uncertain logic circuit including a flip-flop logic circuit which provides digital output values not definitely determined by a digital input value; and

an equalizing circuit which equalizes appearance frequencies of “

0” and

“

1”

in said digital output values from said uncertain logic circuit,

wherein said equalizing circuit includes a circuit configured to operate exclusive OR by using said digital output value from said uncertain logic circuit, and

said uncertain logic circuit alternately repeats a phase for turning OFF a power source of said flip-flop logic circuit over a length of time enough to substantially erase information concerning preceding state of said flip-flop logic circuit and a phase for turning ON said power source of said flip-flop logic circuit, while continuously giving an input signal for holding output of said flip-flop logic circuit at a value maintaining the preceding state, thereby causing said flip-flop logic circuit to output an uncertain digital signal sequence.

15. A random number generating circuit comprising:

an uncertain logic circuit including a flip-flop logic circuit which provides digital output values not definitely determined by a digital input value; and

an equalizing circuit which equalizes appearance frequencies of “

0” and

“

1”

in said digital output values from said uncertain logic circuit,

wherein said uncertain logic circuit includes a plurality of RS-flip-flops, and generates said digital output values by supplying said flip-flops with pulse voltages different in size relative to each other and using outputs from said flip-flops.

16. A random number generating circuit according to claim 15, wherein said uncertain logic circuit provides exclusive OR of outputs from said plurality of flip-flops as said digital output values.

17. A random number generating circuit comprising:

an uncertain logic circuit including a flip-flop logic circuit which provides digital output values not definitely determined by a digital input value; and

an equalizing circuit which equalizes appearance frequencies of “

0” and

“

1”

in said digital output values from said uncertain logic circuit,

wherein said equalizing circuit includes;

a count circuit which counts appearance frequencies of “

0” and

“

1”

output from said flip-flop logic circuit; and

a feedback circuit which gives a feedback signal based on appearance frequencies counted by said count circuit to said flip-flop logic circuit.

18. A random number generating circuit according to claim 17, wherein said uncertain logic circuit alternately repeats a phase for turning OFF a power source of said flip-flop logic circuit over a length of time enough to substantially erase information concerning the preceding state of said flip-flop logic circuit and a phase for turning ON said power source of said flip-flop logic circuit, while continuously giving an input signal for holding the output of said flip-flop type logic circuit at a value maintaining the preceding state, thereby causing said flip-flop logic circuit to output an uncertain digital signal sequence.

19. A random number generating circuit according to claim 17, wherein said flip-flop logic circuit is an RS flip-flop, and wherein said uncertain logic circuit alternately introduces a combination of input data for obtaining the value maintaining the preceding state and a combination of input data causing invalidation of the flip-flop to continuously make the output from said RS flip-flop uncertain.