Information handling system with improved bus system

• US 7,111,099 B2
• Filed: 07/19/2002
• Issued: 09/19/2006
• Est. Priority Date: 07/19/2002
• Status: Expired due to Term

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Martin, Todd, Alexander, Marc D., Mendelow, Matthew B.
• Primary Examiner(s): Dang, Khanh
• Application Number:
  US10/199,076
• Publication Number:
  US 20040015634A1
• Time in Patent Office: 1,523 Days
• Field of Search: 710/305, 710/306, 710313-316, 710/8, 710/62, 710/72, 714/25
• US Class Current: 710/300
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

An information handling system comprises a first bus system comprising a plurality of connection pins wherein at least one pin is unused, at least one control line for controlling or communication with devices of the system, a controllable coupling/de-coupling unit for coupling/de-coupling the control line with the at least one previously unused pin, and a control unit for controlling the coupling/de-coupling unit coupled with the control line.

Claims

1. A bus architecture of a computer system, comprising:

a first bus;

a first slot coupled to the first bus, wherein the first slot has a plurality of pins and wherein at least one of the pins is unused;

a data bus selectively coupled between a device of the computer system and an unused pin of the first slot;

a control line for completing or breaking a connection between the device and the unused pin; and

a control unit coupled to the control line, wherein the control unit is operable to detect the status of the data bus and actuate the control line to complete or break the connection between the device and the unused pin of the first slot.

2. The bus architecture of a computer system of claim 1, wherein the first bus comprises a PCI bus.

3. The bus architecture of a computer system of claim 1, wherein the data bus comprises an SMBus.

4. The bus architecture of a computer system of claim 1, wherein the control unit comprises a sensor for detecting the status of the data bus.

5. The bus architecture of a computer system of claim 1, wherein the device comprises memory and the data bus is coupled between memory and the unused pin of the first slot.

6. The bus architecture of a computer system of claim 1,

wherein the first bus is the PCI bus;

wherein the data bus comprises an SMBus;

wherein the control unit includes a sensor for detecting the status of the data bus; and

wherein the device comprises memory and the data bus is coupled between memory and the unused pin of the first slot.

7. A method for managing the unused pins of a bus of a computer system, comprising:

providing a first bus;

providing a first slot that is coupled to the first bus, wherein the first slot has a plurality of pins and wherein at least one of the pins is unused;

providing a data bus selectively coupled between a device of the computer system and an unused pin of the first slot;

a control line for completing or breaking a connection between the device and the unused pin; and

providing a control unit coupled to the control line, wherein the control unit detects the status of the data bus and actuates the control line to complete or break the connection between the device and the unused pin of the first slot.

8. The method for managing the unused pins of a bus of a computer system of claim 7, wherein the first bus comprises a PCI bus.

9. The method for managing the unused pins of a bus of a computer system of claim 7, wherein the data bus comprises an SMBus.

10. The method for managing the unused pins of a bus of a computer system of claim 7, wherein the device comprises memory and the data bus is coupled between memory and the unused pin of the first slot.

11. The method for managing the unused pins of a bus of a computer system of claim 7,

wherein the first bus is the PCI bus;

wherein the data bus comprises an SMBus; and

wherein the device comprises memory and the data bus is coupled between memory and the unused pin of the first slot.