Method and system for port numbering in an interconnect device

• US 7,111,101 B1
• Filed: 05/07/2003
• Issued: 09/19/2006
• Est. Priority Date: 05/07/2003
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Bourke, Daniel, Chou, Norman C., Vajjhala, Prasad
• Primary Examiner(s): Perveen, Rehana
• Assistant Examiner(s): MISIURA, BRIAN THOMAS
• Application Number:
  US10/431,993
• Time in Patent Office: 1,231 Days
• Field of Search: None
• US Class Current: 710/305
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/253 using establishment or release of connections between ports
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/358 Infiniband Switches

Abstract

A method of port numbering in an interconnect device includes loading a port configuration value from a memory device. One or more ports and subports are enabled according to the configuration value. Contiguous logical port numbers are assigned to the one or more ports and subports included in the interconnect device. A mapping request is received; and a mapped response associated with the mapping request is provided to an entity.

Claims

1. A method of port numbering in an interconnect device, comprising:

loading a port configuration value from a memory device;

enabling one or more ports and subports according to the configuration value;

assigning contiguous logical port numbers to the one or more ports and subports included in the interconnect device;

receiving a mapping request; and

providing a mapped response associated with the mapping request to an entity.

2. The method of claim 1, wherein the mapping request is a logical bit vector and the mapped response is a physical bit vector.

3. The method of claim 1, wherein the mapping request is a physical bit vector and the mapped response is a logical bit vector.

4. The method of claim 1, wherein the mapping request is a logical port number and the mapped response is a physical port number.

5. The method of claim 1, wherein the mapping request is a physical port number and the mapped response is a logical port number.

12. The interconnect device of claim 1, wherein the mapping request is a logical bit vector and the mapped response is a physical bit vector.

6. A system for port numbering in an interconnect device, comprising:

means for loading a port configuration value from a memory device;

means for enabling one or more ports and subports according to the configuration value;

means for assigning contiguous logical port numbers to the one or more ports and subports included in the interconnect device;

means for receiving a mapping request; and

means for providing a mapped response associated with the mapping request to an entity.

7. The system of claim 6, wherein the mapping request is a logical bit vector and the mapped response is a physical bit vector.

8. The system of claim 6, wherein the mapping request is a physical bit vector and the mapped response is a logical bit vector.

9. The system of claim 6, wherein the mapping request is a logical port number and the mapped response is a physical port number.

10. The system of claim 6, wherein the mapping request is a physical port number and the mapped response is a logical port number.

11. An interconnect device comprising:

a memory device; and

a preprocessor, wherein the preprocessor loads a port configuration value from the memory device;

enables one or more ports and subports according to the configuration value;

assigns contiguous logical port numbers to the one or more ports and subports included in the interconnect device;

receives a mapping request; and

provides a mapped response associated with the mapping request to an entity.

13. The interconnect device of claim 11, wherein the mapping request is a physical bit vector and the mapped response is a logical bit vector.

14. The interconnect device of claim 11, wherein the mapping request is a logical port number and the mapped response is a physical port number.

15. The interconnect device of claim 11, wherein the mapping request is a physical port number and the mapped response is a logical port number.

16. A computer-readable storage medium having stored thereon a plurality of instructions, said plurality of instructions when executed, causing said computer to perform:

loading a port configuration value from a memory device;

enabling one or more ports and subports according to the configuration value;

assigning contiguous logical port numbers to the one or more ports and subports included in the interconnect device;

receiving a mapping request; and

providing a mapped response associated with the mapping request to an entity.

17. The computer-readable medium of claim 16, wherein the mapping request is a logical bit vector and the mapped response is a physical bit vector.

18. The computer-readable medium of claim 16, wherein the mapping request is a physical bit vector and the mapped response is a logical bit vector.

19. The computer-readable medium of claim 16, wherein the mapping request is a logical port number and the mapped response is a physical port number.

20. The computer-readable medium of claim 16, wherein the mapping request is a physical port number and the mapped response is a logical port number.