Device and method for performing information processing using plurality of processors
First Claim
1. An information processing device which processes information using a plurality of processors, comprising:
- one or more first processors that have one or a plurality of first local memories;
one or more second processors which performs one of directly writing write information into a target first local memory that a target first processor, selected from among said first processors, has, and directly reading read information from said target first local memory;
address map memory means for storing a first address map in which the first local memory addresses for each of said one or more first processors are recorded,wherein each of said one or more second processors performs one of acquiring the first local memory address of said target first processor from said first address map, writing said write information into the acquired first local memory address, and reading said read information from the acquired first local memory address; and
a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor,wherein said relay device comprises;
a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, andwherein when transferring said write information, said relay device selectively performs an operation of said transfer after said write information is temporarily stored in one or more of said write information storage regions of said relay memory, or an operation of said transfer without storing said write information in said relay memory.
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Abstract
The present invention makes it possible to transfer information between processors by a method that places little burden on the reception side processors. The information processing device is a device that processes information using a plurality of processors, comprising one or more first processors that have one or a plurality of local memories, and one or more second processors that write write information directly into the local memory that the target first processor has. The second processors store address maps in which local memory addresses for the first processors are recorded; these second processors acquire local memory addresses from these address maps, and write write information into the acquired local memory addresses.
28 Citations
33 Claims
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1. An information processing device which processes information using a plurality of processors, comprising:
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one or more first processors that have one or a plurality of first local memories; one or more second processors which performs one of directly writing write information into a target first local memory that a target first processor, selected from among said first processors, has, and directly reading read information from said target first local memory; address map memory means for storing a first address map in which the first local memory addresses for each of said one or more first processors are recorded, wherein each of said one or more second processors performs one of acquiring the first local memory address of said target first processor from said first address map, writing said write information into the acquired first local memory address, and reading said read information from the acquired first local memory address; and a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor, wherein said relay device comprises; a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, and wherein when transferring said write information, said relay device selectively performs an operation of said transfer after said write information is temporarily stored in one or more of said write information storage regions of said relay memory, or an operation of said transfer without storing said write information in said relay memory. - View Dependent Claims (2, 3, 4, 8, 9, 10, 22, 28)
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5. An information processing device which processes information using a plurality of processors, comprising:
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one or more processors that have one or a plurality of first local memories; one or more second processors which performs one of directly writing write information into a target first local memory that a target first processor, selected from among said first processors, has, and directly reading read information from said target first local memory; address map memory means for storing a first address map in which the first local memory addresses for each of said one or more first processors are recorded, wherein each of said one or more second processors performs one of acquiring the first local memory address of said target first processor from said first address map, writing said write information into the acquired first local memory address, and reading said read information from the acquired first local memory address; a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor, wherein said relay device comprises; a relay memory, and wherein when transferring said write information, said relay device selectively performs an operation of said transfer after said write information is temporarily stored in said relay memory, or an operation of said transfer without storing said write information in said relay memory, and wherein one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations are provided in said relay memory, and when temporarily storing the received write information in the relay memory, the relay device stores this write information in a target write information storage region corresponding to the transmission source or transmission destination, and in such cases, furthermore, if the amount of information accumulated in the target write information storage region exceeds a second threshold value, notification of exceeding the second threshold value, which indicates that this threshold value has been exceeded, is transmitted to a specified second device, this second device selectively executes the operation of a direct write system in which said write information is directly written into the target local memory, or the operation of an indirect write system which is devised so that said write information is stored in the relay memory, and so that said target first processor can acquire this write information from the relay memory, and when said notification of exceeding the second threshold value is not received, the write information is transmitted by said direct write system, while when said notification of exceeding the second threshold value is received, the write information is transmitted by said indirect write system. - View Dependent Claims (7)
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6. An information processing device which processes information using a plurality of processors, comprising:
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one or more first processors that have one or a plurality of first local memories; one or more second processors which performs one of directly writing write information into a target first local memory that a target first processor, selected from among said first processors, has, and directly reading read information from said target first local memory; address map memory means for storing a first address map in which the first local memory addresses for each of said one or more first processors are recorded, wherein each of said one or more second processors performs one of acquiring the first local memory address of said target first processor from said first address map, writing said write information into the acquired first local memory address, and reading said read information from the acquired first local memory address; a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor, wherein said relay device comprises; a relay memory, and wherein when transferring said write information, said relay device selectively performs an operation of said transfer after said write information is temporarily stored in said relay memory, or an operation of said transfer without storing said write information in said relay memory, wherein one or more write information storage regions respectively corresponding to one or more transmission sources or transmission destinations of the write information are provided in said relay memory, and when temporarily storing the received write information in the relay memory, the relay device stores this write information in the target write information storage region corresponding to the transmission source or transmission destination, and in such cases, furthermore, if the amount of information accumulated in said target write information storage region exceeds a first threshold value, a notification of exceeding the first threshold value, which indicates that this threshold value has been exceeded, is transmitted to a specified second device, and the second device that receives said notification of exceeding the first threshold value reduces the frequency with which write information is issued or the amount of write information that is issued to said target local memory or said target first processor, and wherein if the amount of information accumulated in said target write information storage region exceeds the second threshold value that is larger than said first threshold value, the relay device transmits a notification of exceeding the second threshold value, which indicates that this threshold value has been exceeded, to said second device, said second device selectively executes the operation of a direct write system in which the write information is directly written into the target local memory, or the operation of an indirect write system which is devised so that the write information is stored in the relay memory, and so that said target first processor can acquire this write information from the relay memory, and when said notification of exceeding the second threshold value is not received, even though the notification of exceeding the first threshold value is received, the write information is transmitted by said direct write system, while when said notification of exceeding the second threshold value is received, said direct write system is stopped, and the write information is transmitted by said indirect write system.
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11. A memory control device which comprises a plurality of microprocessors and a physical or logical memory device, and which performs memory control of the storage of information from host devices in said memory device using said plurality of microprocessors, comprising:
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one or more first microprocessors that have one or a plurality of first local memories; one or more second microprocessors; and a first address map memory part that stores a first address map on which the first local memory addresses for each of said one or more first microprocessors are recorded, wherein each of said one or more second microprocessors acquires, from said first address map, a first local memory write address indicating where writing is to be performed in a target first local memory, which a target first microprocessor selected from among said first microprocessors, has, and writes write information into the acquired first local memory write address, a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor, wherein said relay device comprises; a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, and wherein when transferring said write information, the relay device selectively performs an operation of this transfer after the write information has been temporarily stored in one or more of said write information storage regions of the relay memory, or an operation of this transfer without storing the write information in the relay memory. - View Dependent Claims (12, 14, 16, 17, 23, 29)
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13. The memory control device which comprises a plurality of microprocessors and a physical or logical memory device, and which performs memory control of the storage of information from host devices in said memory device using said plurality of microprocessors, comprising:
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one or more first microprocessors that have one or a plurality of first local memories; one or more second microprocessors; a first address map memory part that stores a first address map on which the first local memory addresses for each of said one or more first microprocessors are recorded, wherein each of said one or more second microprocessors acquires, from said first address map, a first local memory write address indicating where writing is to be performed in a target first local memory, which a target first microprocessor selected from among said first microprocessors, has, and writes write information into the acquired first local memory write address; one or a plurality of first devices in which said one or more first microprocessors are mounted; one or a plurality of second devices in which said one or more second microprocessors are mounted; and a relay device which relays communications between said one or a plurality of first devices and said one or a plurality of second devices; wherein one or more local storage regions that respectively correspond to said one or more second microprocessors are provided in said first local memories, first local memory addresses of the one or more local storage regions that respectively correspond to said one or more first microprocessors are recorded on said first address map, each of said one or more second microprocessors can be connected via the relay device so as to be able to respectively communicate with said one or more first microprocessors by one or more logical or physical paths, and furthermore, when outputting said write information, the second microprocessors acquire the first local memory address of the first local storage region corresponding to said target first processor from said first address map, and output write information which has first transmission destination information that includes said acquired first local memory address, the relay device stores one or more sets of second transmission destination information that respectively correspond to said one or more paths, and when transferring the received write information, the relay device specifies the target path based on said first and second transmission destination information, and transmits the write information to said target first device via the specified target path, and the target first device writes the write information received from the relay device into the first local memory address that is included in the write information wherein said relay device comprises; a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, and wherein when transferring said write information, the relay device selectively performs an operation of this transfer after the write information has been temporarily stored in one or more of said write information storage regions of the relay memory or an operation of this transfer without storing the write information in the relay memory. - View Dependent Claims (15)
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18. A memory control device which comprises a plurality of microprocessors and a physical or logical memory device, and which controls the storage of information from host devices in said memory device using said plurality of microprocessors, this memory control device comprising:
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one or more first microprocessors that have one or a plurality of first local memories; one or more second microprocessors that have one or a plurality of second local memories; a first address map memory means for storing a first address map on which first local memory addresses for each of said one or more first microprocessors are recorded; and a second address map memory means for storing a second address map on which second local memory addresses for each of said one or more second microprocessors are recorded; wherein a target second microprocessor selected from among said second microprocessors acquires, from the first address map, a first local memory write address indicating where writing is to be performed in a target first local memory which a target first microprocessor selected from among said first microprocessors has, and writes a read command into the acquired first local memory write address, and wherein in response to the read command that is written into the first local memory write address, the target first microprocessor acquires, from the second address map, the second local memory write address of the target second microprocessor that originated said read command, reads out read information in the first local memory, and writes the read information into the acquired second local memory write address, a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor, wherein said relay device comprises; a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, and wherein when transferring said write information, the relay device selectively performs an operation of this transfer after the write information has been temporarily stored in one or more of said write information storage regions of the relay memory, or an operation of this transfer without storing the write information in the relay memory. - View Dependent Claims (24, 30)
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19. An information processing method which processes information using a plurality of processors, comprising the steps in which:
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each of one or more second microprocessors acquires a local memory address of a target first processor from an address map in which local memory addresses for each of one or more first processors having one or a plurality of local memories are recorded; each of said one or more second processors performs one of writing write information into said acquired local memory address, and reading read information from said acquired local memory address, and a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor, wherein said relay device comprises; a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, and wherein when transferring said write information, said relay device selectively performs an operation of said transfer after said write information is temporarily stored in one or more of said write information storage regions of said relay memory, or an operation of said transfer without storing said write information in said relay memory. - View Dependent Claims (25, 31)
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20. An information processing device which processes information using a plurality of processors, comprising:
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one or more first processors that have one or a plurality of first local memories; one or more second processors which performs one of directly writing write information into a target first local memory that a target first processor selected from among said first processors has, and directly reading read information from said target first local memory; and a relay device which receives said write information from said one or more second processors and transfers the write information to said target first processor, Wherein said relay device comprises a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, and wherein when transferring said write information, said relay device selectively performs an operation of said transfer after said write information is temporarily stored in one or more of said write information storage regions of said relay memory, or an operation of said transfer without storing said write information in said relay memory. - View Dependent Claims (26, 32)
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21. An information processing method which processes information using a plurality of processors, comprising the steps in which:
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each of one or more second microprocessors acquires a local memory address of a target first processor from an address map on which local memory addresses for each of one or more first processors having one or a plurality of local memories are recorded; and each of said one or more second processors writes write information into said acquired local memory address, and/or reads read information from said acquired local memory address; and a relay device receives said write information from said one or more second processors and transfers the write information to said target first processor, wherein said relay device comprises a relay memory having one or more write information storage regions respectively corresponding to said one or more transmission sources or transmission destinations, and when transferring said write information, said relay device selectively performs an operation of said transfer after said write information is temporarily stored in one or more of said write information storage regions of said relay memory or an operation of said transfer without storing said write information in said relay memory. - View Dependent Claims (27, 33)
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Specification