TLB miss fault handler and method for accessing multiple page tables

• US 7,111,145 B1
• Filed: 03/25/2003
• Issued: 09/19/2006
• Est. Priority Date: 03/25/2003
• Status: Expired due to Term

• Current Assignee: VMware, Inc. (Broadcom, Inc.)
• Original Assignee: VMware, Inc. (Broadcom, Inc.)
• Inventors: Munoz, Alberto J., Chen, Xiaoxin
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): SONG, HUA JASMINE
• Application Number:
  US10/397,030
• Time in Patent Office: 1,274 Days
• Field of Search: 711/6, 711/202, 711/203, 711205-207, 710/9
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Claims

1. A computer program embodied in a tangible medium, the computer program being executable in a virtual computer system, the virtual computer system comprising a virtual machine monitor having a first address space and a virtual machine having a second address space, the virtual computer system further comprising a first page table for mapping addresses from the first address space and a second page table for mapping addresses from the second address space, the computer program comprising:

a first routine for responding to a TLB Miss fault resulting from an attempted memory access, the first routine executing in the same context in which the TLB Miss fault occurred; and

a second routine executing in a different context from the first routine, wherein;

the first routine determines an operating state in which the virtual computer system was operating when the TLB Miss fault occurred,

the first routine receives an address space identifier which indicates if the attempted memory access was to the first address space or the second address space,

the first routine uses the operating state and the address space identifier to determine if the attempted memory access is permitted, and

if the attempted memory access is permitted, the first routine uses the address space identifier to determine if the attempted memory access was to the first address space or the second address space, and, if the attempted memory access was to the first address space, the first routine attempts to find a translation for the attempted memory access in the first page table, or, if the attempted memory access was to the second address space, the first routine attempts to find a translation for the attempted memory access in the second page table, or

the attempted memory access is not permitted, a context switch is performed and execution switches to the second routine for responding to the impermissible attempted memory access.

2. The computer program of claim 1, in which the operating state in which the virtual computer system was operating is an execution mode of the virtual machine monitor.

3. The computer program of claim 2, in which a first execution mode is an emulation mode and a second execution mode is a direct execution mode.

4. The computer program of claim 3, in which the emulation mode is a binary translation mode.

5. The computer program of claim 3, in which the attempted memory access is permitted if the operating state was the emulation mode and the attempted memory access was to either the first address space or the second address space, or if the operating state was the direct execution mode and the attempted memory access was to the second address space.

6. The computer program of claim 5, in which the first address space is contained in one or more numbered memory regions and, if the operating state was the direct execution mode and the attempted memory access was to a first region of the first address space, the first region is switched to a different region number.

7. The computer program of claim 6, in which a third execution mode is a monitor mode.

8. The computer program of claim 7, in which the attempted memory access is permitted if the operating state was the monitor mode and the attempted memory access was to the first address space, and the attempted memory access is not permitted if the operating state was the monitor mode and the attempted memory access was to the second address space.

9. The computer program of claim 8, in which the virtual machine has virtual physical memory which is mapped into the first address space.

10. The computer program of claim 1, in which the address space identifier comprises one or more bits of a virtual address for the attempted memory access.

11. The computer program of claim 10, in which the address space identifier specifies a region number.

12. The computer program of claim 1, in which, if the attempted memory access is permitted and the attempted memory access was to the second address space but a translation for the attempted memory access is not found in the second page table, a context switch is performed and execution switches to a third routine, the third routine attempting to find a translation for a virtual address of the attempted memory access in a virtual TLB of the virtual machine.

13. The computer program of claim 12, in which, if a translation for the virtual address of the attempted memory access is not found in the virtual TLB, a TLB Miss fault is forwarded to a guest operating system in the virtual machine.

14. In a virtual computer system comprising a virtual machine monitor having a first address space and a virtual machine having a second address space, the virtual machine monitor having an emulation mode that may access both the first and the second address spaces and a direct execution mode that may only access the second address space, a method for providing virtual address translations for both the emulation mode and the direct execution mode, the method comprising:

providing a first page table having translations for the first address space;

providing a second page table having translations for the second address space; and

in response to a TLB Miss fault, performing the following steps;

determining whether the virtual machine monitor was in the emulation mode or the direction execution mode when the TLB Miss fault occurred;

determining whether the TLB Miss fault resulted from an attempt to access the first address space or the second address space; and

;

if the virtual machine monitor was in the emulation mode and the attempted access was to the first address space, obtaining the virtual address translation from the first page table;

if the virtual machine monitor was in the emulation mode and the attempted access was to the second address space, obtaining the virtual address translation from the second page table;

or if the virtual machine monitor was in the direct execution mode and the attempted access was to the second address space, obtaining the virtual address translation from the second page table.

15. The method of claim 14, wherein the steps of determining whether the virtual machine monitor was in the emulation mode or the direction execution mode, determining whether the attempted access was to the first address space or the second address space, and obtaining the virtual address translation from the first page table or the second page table are all performed within a single context in an interrupt handler.

16. The method of claim 14, wherein if the virtual machine monitor was in the direct execution mode and the attempted access was to the first address space, switching execution to a different routine that switches the first address space to a different region number.

17. The method of claim 14, further comprising providing a TLB for holding translations for both the first address space and the second address space, the TLB being checked for the virtual address translation before a TLB Miss fault is generated.

18. The method of claim 17, further comprising providing a page table walker for checking for the virtual address translation before a TLB Miss fault is generated, the page table walker being configured to check the second page table when the virtual machine monitor is in either the emulation mode or the direct execution mode.

19. The method of claim 18, in which the virtual machine monitor also has a monitor mode that may only access the first address space, the method further providing virtual address translations for the monitor mode, the method further comprising determining whether the virtual machine monitor was in the monitor mode when the TLB Miss fault occurred and, if the virtual machine monitor was in the monitor mode and the attempted access was to the first address space, obtaining the virtual address translation from the first page table.

20. A method of emulating a guest instruction in a virtual computer system, the virtual computer system comprising a virtual machine monitor having a first address space and a virtual machine having a second address space, the method comprising:

using one or more references to the first address space to retrieve one or more emulation instructions, wherein execution of the emulation instructions emulates the execution of the guest instruction;

using one or more references to the second address space to retrieve one or more data for use with the emulation instructions;

providing a first page table for translations for the first address space;

providing a second page table for translations for the second address space; and

in response to an attempted memory access, using an address space identifier to determine if the attempted memory access was to the first address space or to the second address space, and, if the attempted memory access was to the first address space, using the first page table to obtain a translation for the attempted memory access, or, if the attempted memory access was to the second address space, using the second page table to obtain a translation for the attempted memory access.

21. The method of claim 20, wherein the guest instruction is emulated using binary translation techniques.

22. The method of claim 20, in which the address space identifier comprises one or more bits of a virtual address for the attempted memory access.

23. The method of claim 22, in which the address space identifier specifies a region number.

24. The method of claim 20, in which the steps of using an address space identifier to determine if the attempted memory access was to the first address space or to the second address space, and, if the attempted memory access was to the first address space, using the first page table to obtain a translation for the attempted memory access, or, if the attempted memory access was to the second address space, using the second page table to obtain a translation for the attempted memory access are further in response to a TLB Miss fault.

25. The method of claim 24, further comprising, providing a TLB which is checked for a translation for the attempted memory access prior to any TLB Miss fault, and inserting translations for both the first and the second address spaces into the TLB.

26. The method of claim 25, further comprising, providing a page table walker and configuring the page table walker to check the second page table for a translation for the attempted memory access prior to any TLB Miss fault.

27. The method of claim 25, further comprising, providing a page table walker and configuring the page table walker to check the first page table for a translation for the attempted memory access prior to any TLB Miss fault.