Digital signal processor computation core with input operand selection from operand bus for dual operations

• US 7,111,155 B1
• Filed: 05/12/2000
• Issued: 09/19/2006
• Est. Priority Date: 05/12/1999
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Anderson, William C., Fridman, Jose, Edmondson, John, Hoffman, Marc, Rivin, Russell L.
• Primary Examiner(s): Fleming, Fritz
• Assistant Examiner(s): DOLLINGER, TONIA LYNN MEONSKE
• Application Number:
  US09/570,108
• Time in Patent Office: 2,321 Days
• Field of Search: 712/210, 712/32, 712/208, 712/204, 712/225, 712/221, 712/33, 712/226
• US Class Current: 712/225
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.

Claims

1. A computation unit comprising:

a register file for storing operands;

first and second operand buses coupled to said register file, each simultaneously carrying a high operand and a low operand;

a first execution unit for performing a first operation on first and second operands of a specified word width in response to an instruction, the specified word width of the first and second operands being less than a width of each operand bus;

a first data selector, responsive to a first operand select value contained in a first field of the instruction, for selecting the first operand from the high operand and the low operand on said first operand bus and for supplying the first operand to said first execution unit;

a second data selector, responsive to a second operand select value contained in a second field of the instruction, for selecting the second operand from the high operand and the low operand on said second operand bus and for supplying the second operand to said first execution unit;

a second execution unit for performing a second operation on third and fourth operands of the specified word width in response to the instruction, the specified word width of the third and fourth operands being less than the width of each operand bus;

a third data selector, responsive to a third operand select value contained in a third field of the instruction, for selecting the third operand from the high operand and the low operand on said first operand bus and for supplying the third operand to said second execution unit; and

a fourth data selector, responsive to a fourth operand select value contained in a fourth field of the instruction, for selecting the fourth operand from the high operand and the low operand on said second operand bus and for supplying the fourth operand to said second execution unit, wherein each of the data selectors selects a subset of bits from a single operand bus, wherein the first and third data selectors select respective subsets of bits from the first operand bus and wherein the second and fourth data selectors select respective subsets of bits from the second operand bus.

2. A computation unit as defined in claim 1, wherein said first and second execution units each comprise an arithmetic logic unit, a multiplier and an accumulator.

3. A computation unit as defined in claim 2, wherein said first execution unit further comprises a shifter.

4. A computation unit as defined in claim 1, wherein said register file comprises first and second register banks, each having two read ports and two write ports.

5. A computation unit as defined in claim 1, wherein said register file comprises a single register bank having four read ports and four write ports.

6. A computation unit as defined in claim 1, further comprising first and second result buses coupled between said first and second execution units and said register file for transferring results of the first and second operations to the register file.

7. A computation unit as defined in claim 1, wherein each of said high and low operands is a 16-bit operand.

8. A computation unit as defined in claim 1, configured for performing digital signal processor computations.

9. A computation unit as defined in claim 1, wherein each of said first and second operand buses is a 32-bit bus and wherein each of said high and low operands is a 16-bit operand.