Method and system for external clock to obtain multiple synchronized redundant computers

• US 7,111,195 B2
• Filed: 02/25/2003
• Issued: 09/19/2006
• Est. Priority Date: 02/25/2002
• Status: Active Grant

• Current Assignee: ABB Schweiz AG (ABB Limited)
• Original Assignee: General Electric Company
• Inventors: Premerlani, William James, Berkcan, Ertugrul, Andarawis, Emad Andarawis, Schnore, Austars Raymond Jr., Topka, Terry Michael, Pearlman, Marc Robert
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): MASKULINSKI, MICHAEL C
• Application Number:
  US10/373,630
• Publication Number:
  US 20030212835A1
• Time in Patent Office: 1,302 Days
• Field of Search: 714/12, 713/375, 709/248
• US Class Current: 714/12
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: H01H 2300/03 Application domotique, e.g. for house automation, bus connected switches, sensors, loads or intelligent wiring
• CPC Class Codes: H02H 1/0061 concerning transmission of signals transmission of measured quantities or switching orders; sectionalised protection involving signal transmission between at least two stations H02H7/261; comparison of the voltage or current values at two spaced portions of a single system H02H3/28; transferring the output of a sensing member to another variable G01D5/00; electrical measuring arrangements using modulation of electromagnetic waves, e.g. light beams G01R15/24, G01R15/26
• CPC Class Codes: H02H 3/006 Calibration or setting of parameters
• CPC Class Codes: H02H 3/05 with means for increasing reliability, e.g. redundancy arrangements for logic circuits H03K19/003
• CPC Class Codes: H02H 7/263 involving transmissions of measured values comparison of currents or voltages using pilot wires H02H3/30
• CPC Class Codes: H02J 13/00001 characterised by the display of information or by user interaction, e.g. supervisory control and data acquisition systems [SCADA] or graphical user interfaces [GUI]
• CPC Class Codes: H02J 13/00007 using the power network as support for the transmission
• CPC Class Codes: H02J 13/00009 using pulsed signals
• CPC Class Codes: H02J 13/00012 using an auxiliary transmission line
• CPC Class Codes: H02J 13/00016 using a wired telecommunication network or a data transmission bus
• CPC Class Codes: H02J 13/00018 using phone lines
• CPC Class Codes: H02J 13/00028 involving the use of Internet protocols
• CPC Class Codes: H02J 13/00034 the elements or equipment being or involving an electric power substation
• CPC Class Codes: H02J 13/00036 the elements or equipment being or involving switches, relays or circuit breakers circuits for indication of single switches H01H9/167
• CPC Class Codes: H02J 13/0004 involved in a protection system
• CPC Class Codes: H02J 2203/20 Simulating, e g planning, reliability check, modelling or computer assisted design [CAD]
• CPC Class Codes: H02J 2310/64 The condition being economic, e.g. tariff based load management
• CPC Class Codes: H02J 3/0012 Contingency detection
• CPC Class Codes: H02J 3/007 Arrangements for selectively connecting the load or loads to one or several among a plurality of power lines or power sources for providing uninterruptable power supply H02J9/00
• CPC Class Codes: Y02B 70/30 : Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
• CPC Class Codes: Y02B 70/3225 : Demand response systems, e.g. load shedding, peak shaving
• CPC Class Codes: Y02B 90/20 : Smart grids as enabling technology in buildings sector smart grids supporting the management or operation of end-user stationary applications in general, or like technologies with no associated climate change mitigation effect Y04S20/00
• CPC Class Codes: Y04S 10/40 : Display of information, e.g. of data or controls
• CPC Class Codes: Y04S 20/14 : Protecting elements, switches, relays or circuit breakers
• CPC Class Codes: Y04S 20/20 : End-user application control systems
• CPC Class Codes: Y04S 20/221 : General power management systems
• CPC Class Codes: Y04S 20/222 : Demand response systems, e.g. load shedding, peak shaving
• CPC Class Codes: Y04S 40/121 : using the power network as support for the transmission
• CPC Class Codes: Y04S 40/124 : using wired telecommunication networks or data transmission busses
• CPC Class Codes: Y04S 50/10 : Energy trading, including energy flowing from end-user application to grid

Abstract

A method for synchronizing a plurality of processors within a computer system is provided. The computer system includes a plurality of processors that are each communicatively coupled to a respective network wherein each network is independent of each other network. The method includes receiving a plurality of input signals at a first rate from at least one source, transmitting the input signals to a reference object, and transforming the input signal to a known temporal reference. The apparatus is configured to receive a plurality of input signals at a first rate from at least one source, transmit the input signals to a reference object, and transform the input signal to a known temporal reference.

Claims

1. A method for synchronizing a plurality of processors within a computer system wherein the computer system includes a plurality of processors, each processor communicatively coupled to a respective network that is independent of each other network, said method comprising:

receiving a plurality of input signals at a first rate from at least one source;

transmitting each input signal of the plurality of input signals to a reference object;

transforming each input signal to a known temporal reference;

generating a reference signal in each processor based on the transformed input signal wherein each reference signal is in a known temporal relationship with a reference signal in each other processor;

executing a plurality of processes in each processor based on each respective reference signal, wherein the computer system includes a plurality of node electronic units, each of the plurality of node electronics units communicatively coupled to at least one network;

transmitting a transreference signal over the network, the transreference signal based on the reference signal;

executing node electronics unit internal processes based on a first clock;

receiving the transreference signal at the node electronics unit; and

executing a referencing process when the transreference signal is received, wherein executing a referencing process further comprises;

determining a status of the transreference signal based on the first clock;

recording a receipt time of the transreference signal based on the first clock;

determining a first clock error based on at least one of the first clock time, the transreference signal, the determined status of the transreference signal, and the order of preference of the processor from which the transreference signal was received;

adjusting the first clock based on the error calculation; and

synchronizing node electronics unit processes based on the adjusted first clock.

2. A method in accordance with claim 1 wherein executing a referencing process comprises executing a referencing process using at least one of an internal clock, and an external clock.

3. A method in accordance with claim 2 wherein executing a referencing process comprises executing a referencing process based on the transreference signal as the clock.

4. A method in accordance with claim 1 wherein adjusting the first clock based on the error calculation comprises adjusting the first clock using a phase lock loop (PLL).

5. A method in accordance with claim 1 wherein adjusting the first clock based on the error calculation comprises setting the clock from the transreference signal.

6. A method in accordance with claim 1 further comprising:

determining a first out-of-sync condition based on the determined error; and

transmitting the first out-of-sync signal to each processor.

7. A method in accordance with claim 6 wherein transmitting the first out-of-sync signal to each processor comprises transmitting the first out-of-sync signal that includes at least one clock value.

8. A method in accordance with claim 6 further comprising determining an out-of-sync signal for each node electronics unit based on at least one of the first out-of-sync signal, and each processor reference signal.

9. A method in accordance with claim 1 wherein each clock includes a clock sequence number, and wherein determining a first clock error based on the transreference signal comprises determining a first clock error based on the transreference signal wherein the transreference signal includes a transreference sequence number.

10. A method for synchronizing a plurality of processors within a computer system, each processor communicatively coupled to a respective network that is independent of each other network, said method comprising:

receiving a plurality of input signals at a first rate from at least one source;

transmitting each input signal of the plurality of input signals to a reference object;

transforming each input signal to a known temporal reference;

generating a reference signal in each processor based on the transformed input signal wherein each reference signal is in a known temporal relationship with a reference signal in each other processor; and

executing a plurality of processes in each processor based on each respective reference signal,

wherein each processor includes a corrector function and wherein the method further comprises determining a status of a first input signal based on the first input signal and each other input signal, and

wherein determining a status of a first input signal comprises at least one of determining a presence of the first input signal within an expected time window, determining an absence of the first input signal, determining an invalid first input signal, and determining a noisy first input signal.

11. A method in accordance with claim 10 wherein said receiving a plurality of input signals comprises receiving a plurality of input signals from at least one of a source internal to the processor, and a source internal to any other of the plurality of processors.

12. A method in accordance with claim 10 wherein said receiving a plurality of input signals comprises receiving a plurality of input sequence numbers.

13. A method in accordance with claim 12 wherein said receiving a plurality of input sequence numbers comprises receiving a plurality of input sequence numbers that are at least six bits long.

14. A method in accordance with claim 12 wherein said receiving a plurality of input sequence numbers comprises receiving a plurality of input sequence numbers that are sixteen bits long.

15. A method in accordance with claim 10 wherein said generating a reference signal comprises generating a reference signal that includes a reference sequence number.

16. A method in accordance with claim 15 wherein said generating a reference signal comprises generating a reference signal that includes a reference sequence number sixty-four bits long.

17. A method in accordance with claim 10 wherein the computer system includes a plurality of node electronic units, each of the plurality of node electronics units communicatively coupled to at least one network, and wherein the method further comprises transmitting a transreference signal over the network, the transreference signal based on the reference signal.

18. A method in accordance with claim 17 wherein the node electronics units include at least one clock, and wherein the method further comprises:

executing node electronics unit internal processes based on a first clock;

receiving the transreference signal at the node electronics unit; and

executing a referencing process when the transreference signal is received.

19. A method in accordance with claim 10 wherein determining an absence of the first input signal comprises using a watchdog timer to determine the absence of the first input signal.

20. A method in accordance with claim 10 further comprising:

determining an input signal error based on the first input signal and each other input signal, and

transmitting an error signal to a respective source; and

adjusting each input signal based on the transmitted error signal.

21. A method in accordance with claim 20 wherein adjusting each input signal comprises adjusting each input signal using a phase lock loop at the input signal source.

22. A method in accordance with claim 20 wherein adjusting each input signal comprises adjusting each input signal by setting the source using one other of the input signals.

23. A method in accordance with claim 10 further comprising generating a reference signal based on a transformed input signal wherein the transformation is modified when at least one of the occurrence of a first event and the occurrence of a transition to an unsatisfactory status of at least one input signal.

24. A method in accordance with claim 23 wherein generating a reference signal comprises replacing each unsatisfactory input signal with an available input signal based on the order of preference of input signals.

25. A method in accordance with claim 23 wherein generating a reference signal comprises generating a reference signal wherein the first event is a loss of at least one input signal.

26. A method for synchronizing a plurality of processors within a computer system wherein the computer system includes a plurality of processors, each processor communicatively coupled to a respective network that is independent of each other network, said method comprising:

receiving a plurality of input signals at a first rate from at least one source;

transmitting each input signal of the plurality of input signals to a reference object;

transforming each input signal to a known temporal reference;

generating a reference signal in each processor based on the transformed input signal wherein each reference signal is in a known temporal relationship with a reference signal in each other processor;

executing a plurality of processes in each processor based on each respective reference signal, wherein each processor includes a corrector function;

determining a status of a first input signal based on the first input signal and each other input signal; and

generating a reference signal based on a transformed input signal wherein the transformation is modified when at least one of the occurrence of a second event and the occurrence of a transition to a satisfactory status of at least one input signal.

27. A method in accordance with claim 26 wherein generating a reference signal comprises replacing an available input signal with a satisfactory input signal based on the order of preference of input signals.

28. A method in accordance with claim 26 wherein generating a reference signal comprises generating a reference signal wherein the second event is a restoration of at least one input signal.

29. A method in accordance with claim 26 wherein generating a reference signal comprises generating a reference signal based on an error signal generated by the corrector function.

30. Apparatus for synchronizing a plurality of processors within a computer system, said computer system comprising a plurality of processors, each said processor communicatively coupled to a respective network that is independent of each other network, said apparatus comprising:

means for receiving a plurality of input signals at a first rate from at least one source;

means for transmitting the input signals to a reference object;

means for transforming the input signal to a known temporal reference;

means for generating a reference signal in each processor based on the transformed input signal wherein each reference signal is in a known temporal relationship with a reference signal in each other processor;

means for executing a plurality of processes in each processor based on each respective reference signal,

wherein said computer system further comprises a plurality of node electronic units, each of said plurality of node electronics units communicatively coupled to at least one network, and wherein the apparatus further comprises means for transmitting a transreference signal over the network, the transreference signal based on the reference signal,

wherein each said node electronics units comprises at least one clock, and wherein said apparatus further comprises;

means for executing node electronics unit internal processes based on a first clock;

means for receiving the transreference signal at the node electronics unit; and

means for executing a referencing process when the transreference signal is received;

means for determining a status of the transreference signal based on the first clock;

means for recording a receipt time of the transreference signal based on the first clock;

means for determining a first clock error based on at least one of the first clock time, the transreference signal, the determined status of the transreference signal, and the order of preference of the processor from which the transreference signal was received;

means for adjusting the first clock based on the error calculation; and

means for synchronizing node electronics unit processes based on the adjusted first clock.

31. Apparatus in accordance with claim 30 further comprising means for executing a referencing process using at least one of an internal clock, and an external clock.

32. Apparatus in accordance with claim 31 further comprising means for executing a referencing process based on the transreference signal as the clock.

33. Apparatus in accordance with claim 30 further comprising means for adjusting the first clock using a phase lock loop (PLL).

34. Apparatus in accordance with claim 30 further comprising means for setting the clock from the transreference signal.

35. Apparatus in accordance with claim 30 further comprising:

means for determining a first out-of-sync condition based on the determined error; and

means for transmitting the first out-of-sync signal to each processor.

36. Apparatus in accordance with claim 35 further comprising means for transmitting the first out-of-sync signal wherein the signal comprises at least one clock value.

37. Apparatus in accordance with claim 35 further comprising means for determining an out-of-sync signal for each node electronics unit based on at least one of the first out-of-sync signal, and each processor reference signal.

38. Apparatus in accordance with claim 30 wherein each clock includes a clock sequence number, and wherein said apparatus further comprises means for determining a first clock error based on the transreference signal wherein the transreference signal includes a transreference sequence number.

39. Apparatus for synchronizing a plurality of processors within a computer system, each processor of said plurality of processors being communicatively coupled to a respective network that is independent of each other network, said apparatus comprising:

means for receiving a plurality of input signals at a first rate from at least one source;

means for transmitting the input signals to a reference object;

means for transforming the input signal to a known temporal reference;

means for generating a reference signal in each processor based on the transformed input signal wherein each reference signal is in a known temporal relationship with a reference signal in each other processor;

means for executing a plurality of processes in each processor based on each respective reference signal;

wherein each processor includes a corrector function and wherein said apparatus further comprises means for determining a status of a first input signal based on the first input signal and each other input signal; and

at least one selected from the groups consisting of;

means for determining a presence of the first input signal within an expected time window, means for determining an absence of the first input signal, means for determining an invalid first input signal, and determine a noisy first input signal, wherein each processor includes a corrector function and wherein said apparatus further comprises means for determining a status of a first input signal based on the first input signal and each other input signal.

40. Apparatus in accordance with claim 39 further comprising means for receiving a plurality of input signals from at least one of a source internal to said processor, and a source internal to any other of said plurality of processors.

41. Apparatus in accordance with claim 39 further comprising means for receiving a plurality of input sequence numbers.

42. Apparatus in accordance with claim 41 further comprising means for receiving a plurality of input sequence numbers that are at least six bits long.

43. Apparatus in accordance with claim 41 further comprising means for receiving a plurality of input sequence numbers that are sixteen bits long.

44. Apparatus in accordance with claim 39 further comprising means for generating a reference signal that includes a reference sequence number.

45. Apparatus in accordance with claim 44 further comprising means for generating a reference signal that includes a reference sequence number sixty-four bits long.

46. Apparatus in accordance with claim 39 wherein said computer system further comprises a plurality of node electronic units, each of said plurality of node electronics units communicatively coupled to at least one network, and wherein the apparatus further comprises means for transmitting a transreference signal over the network, the transreference signal based on the reference signal.

47. Apparatus in accordance with claim 46 wherein each said node electronics units comprises at least one clock, and wherein said apparatus further comprises:

means for executing node electronics unit internal processes based on a first clock;

means for receiving the transreference signal at the node electronics unit; and

means for executing a referencing process when the transreference signal is received.

48. Apparatus in accordance with claim 39 further comprising means for using a watchdog timer to determine the absence of the first input signal.

49. Apparatus in accordance with claim 39 further comprising:

means for determining an input signal error based on the first input signal and each other input signal, and

means for transmitting an error signal to a respective source; and

means for adjusting each input signal based on the transmitted error signal.

50. Apparatus in accordance with claim 49 further comprising means for adjusting each input signal using a phase lock loop at the input signal source.

51. Apparatus in accordance with claim 49 further comprising means for adjusting each input signal by setting the source using one other of the input signals.

52. Apparatus in accordance with claim 39 further comprising means for generating a reference signal based on a transformed input signal wherein the transformation is modified when at least one of the occurrence of a first event and the occurrence of a transition to an unsatisfactory status of at least one input signal.

53. Apparatus in accordance with claim 52 further comprising means for replacing each unsatisfactory input signal with an available input signal based on the order of preference of input signals.

54. Apparatus in accordance with claim 52 wherein the first event is a loss of at least one input signal.

55. Apparatus in accordance with claim 39 further configured to generate a reference signal based on a transformed input signal wherein the transformation is modified when at least one of the a second event occurs, and a transition to a satisfactory status of at least one input signal occurs.

56. Apparatus in accordance with claim 55 further comprising means for replacing an available input signal with a transitioned to satisfactory input signal based on the order of preference of input signals.

57. Apparatus in accordance with claim 55 wherein the second event is a restoration of at least one input signal.

58. Apparatus in accordance with claim 55 further comprising means for generating a reference signal based on an error signal generated by the corrector function.

59. A method for synchronizing a plurality of processors within a computer system, each processor communicatively coupled to a respective network that is independent of each other network, said method comprising:

generating a first input signal in a first timing source, said first timing source being external to said plurality of processors;

generating a second input signal in a second timing source internal to each particular processor;

transmitting said first input signal to a reference object and a correction function in each of said plurality of processors;

transmitting said second input signal to said reference object and said correction function in said particular processor;

transforming said first and second input signals into a transreference signal in said reference object in said particular processor;

determining a timing error signal in said correction function in said particular processor; and

transmitting said timing error signal to said first and second timing sources.

60. A method in accordance with claim 59 further comprising using said transreference signal to drive local processes within said particular processor.

61. A method in accordance with claim 59 further comprising:

transmitting said transreference signal over the network to a plurality of node electronic units in the computer system; and

executing node electronics unit internal processes based on a first clock;

receiving said transreference signal at said plurality of node electronics unit; and

executing a referencing process when said transreference signal is received.