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Method and system for external clock to obtain multiple synchronized redundant computers

  • US 7,111,195 B2
  • Filed: 02/25/2003
  • Issued: 09/19/2006
  • Est. Priority Date: 02/25/2002
  • Status: Active Grant
First Claim
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1. A method for synchronizing a plurality of processors within a computer system wherein the computer system includes a plurality of processors, each processor communicatively coupled to a respective network that is independent of each other network, said method comprising:

  • receiving a plurality of input signals at a first rate from at least one source;

    transmitting each input signal of the plurality of input signals to a reference object;

    transforming each input signal to a known temporal reference;

    generating a reference signal in each processor based on the transformed input signal wherein each reference signal is in a known temporal relationship with a reference signal in each other processor;

    executing a plurality of processes in each processor based on each respective reference signal, wherein the computer system includes a plurality of node electronic units, each of the plurality of node electronics units communicatively coupled to at least one network;

    transmitting a transreference signal over the network, the transreference signal based on the reference signal;

    executing node electronics unit internal processes based on a first clock;

    receiving the transreference signal at the node electronics unit; and

    executing a referencing process when the transreference signal is received, wherein executing a referencing process further comprises;

    determining a status of the transreference signal based on the first clock;

    recording a receipt time of the transreference signal based on the first clock;

    determining a first clock error based on at least one of the first clock time, the transreference signal, the determined status of the transreference signal, and the order of preference of the processor from which the transreference signal was received;

    adjusting the first clock based on the error calculation; and

    synchronizing node electronics unit processes based on the adjusted first clock.

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