Network physical layer with embedded multi-standard CRC generator

• US 7,111,220 B1
• Filed: 03/01/2002
• Issued: 09/19/2006
• Est. Priority Date: 03/01/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Verma, Hare K., Cory, Warren E., Menon, Suresh M., Ghia, Atul V., Sasaki, Paul T., Freidin, Philip M.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Tabone, Jr., John J.
• Application Number:
  US10/090,519
• Time in Patent Office: 1,663 Days
• Field of Search: 714/753, 714/807, 714/808, 370/445, 370/463, 370/473, 370/537, 341/59, 341/58, 710/126, 710/65, 709/248, 709/236, 340/347
• US Class Current: 714/753
• CPC Class Codes: H03M 13/091 Parallel or block-wise CRC computation
• CPC Class Codes: H03M 13/6519 Support of multiple transmission or communication standards
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC

Abstract

Disclosed are methods and structures for preparing data for transmission over a network. In an embodiment consistent with the OSI network model, transmit and receive CRC generators are moved from the link layer to the physical layer, which frees up valuable programmable logic resources when a programmable logic device is employed to perform the functions of the link layer. The CRC generators of the physical layer comply with a plurality of network communication standards.

Claims

1. A method of transmitting network data, the method comprising:

assembling the data into a plurality of data frames in a link layer implemented in programmable logic of an integrated circuit;

encapsulating the plurality of data frames into data packets in a physical layer implemented in application-specific logic of the integrated circuit, each data packet having a start field identifying the start of the packet and a data field including a data frame;

appending idle data to each data packet in the physical layer to form packet assemblies;

performing, for each packet assembly, a cyclic redundancy check (CRC) of the data frame in a sublayer of the physical layer separate from a physical layer interface to obtain a CRC value; and

adding, for each packet assembly, a CRC value to the data packet in a sublayer of the physical layer.

2. The method of claim 1, further comprising:

evaluating each packet assembly to obtain a disparity value; and

if the disparity value for a packet assembly indicates an incorrect disparity, changing the packet assembly.

3. The method of claim 2, wherein changing the packet assembly comprises changing the idle data.

4. The method of claim 2, wherein each data packet includes an end-of-packet field, and wherein changing the packet assembly comprises changing the end-of-packet field.

5. The method of claim 1, wherein the idle data comprises a comma character.

6. The method of claim 5, wherein the comma character includes five consecutive identical bits.

7. The method of claim 6, wherein the five consecutive identical bits are logic zeros.

8. The method of claim 1, wherein appending the idle data occurs before performing the CRC of the data frame.

9. The method of claim 1, further comprising adding an extension field to a data frame before encapsulating the data frame into a data packet.

10. The method of claim 1, further comprising programming programmable logic to assemble the data into a plurality of data frames.

11. The method of claim 10, wherein the programmable logic does not perform the CRC.

12. The method of claim 10, wherein the CRC is performed using application-specific logic.

13. A network physical layer coupled to transmit data frames in a programmable logic device and instantiated in application-specific logic of the programmable logic device, the physical layer comprising:

a data node coupled to receive a plurality of data packets from a link layer implemented in programmable logic of the programmable logic device, each data packet including a data frame; and

a CRC generator in a sublayer of the physical layer separate from a physical layer interface and coupled to the data node to perform a CRC, for each data packet, on the data frame to provide a CRC value and to insert the CRC value into the data packet.

14. The physical layer of claim 13, wherein the data node is further coupled to receive idle data.

15. The physical layer of claim 14, wherein a data packet and idle data collectively form a packet assembly, the physical layer further comprising an encoder coupled to receive the packet assembly and to provide a disparity value that is a function of the packet assembly.

16. The physical layer of claim 15, further comprising a packet-assembly modifier connected to the encoder and coupled to receive the disparity value and to modify the packet assembly in response to the disparity value.

17. The physical layer of claim 16, wherein the packet-assembly modifier outputs a modified packet assembly having modified idle data.

18. The physical layer of claim 16, wherein the disparity value may be positive or negative.

19. The physical layer of claim 18, wherein the packet-assembly modifier modifies the idle data in response to the positive disparity value.

20. The physical layer of claim 18, wherein the packet-assembly modifier leaves unmodified the idle data in response to the negative disparity value.

21. The physical layer of claim 13, wherein the CRC generator further comprises a first module enabling a first communication standard and a second module enabling a second communication standard.

22. The physical layer of claim 13, wherein the CRC generator further comprises a force-error input terminal.

23. The physical layer of claim 22, wherein the force-error input terminal is coupled to receive a test signal for inducing the CRC generator to produce an error.

24. A programmable logic device comprising:

an array of configurable logic blocks comprising a link layer implemented in programmable logic for transmitting network data; and

a network physical layer instantiated in hard logic and coupled to receive network data comprising a plurality of data frames from the link layer;

wherein the physical layer comprises a CRC generator performing a cyclic redundancy check on each data frame of the plurality of data frames in a sublayer of the physical layer separate from a physical layer interface.

25. The programmable logic device of claim 24, wherein the CRC generator performs a plurality of CRC functions to support a plurality of communication standards.

26. The programmable logic device of claim 24, further comprising a data encapsulator coupled to receive a data frame and provide a data packet based on the data frame, wherein the CRC generator performs a CRC on at least a portion of the data frame to obtain a CRC value and to insert the CRC value into the data packet.

27. The programmable logic device of claim 26, wherein the data encapsulator adds idle data to the packet to form a packet assembly, the programmable logic device further comprising a packet-assembly modifier coupled to modify the packet assembly based in part on the CRC value.

28. The programmable logic device of claim 27, wherein the packet-assembly modifier modifies the idle data.

29. The programmable logic device of claim 24, wherein the CRC generator further comprises a force-error input terminal.

30. The programmable logic device of claim 29, wherein the force-error input terminal is coupled to receive a test signal for inducing the CRC generator to produce an error.

31. A network receiver coupled to receive data and instantiated in application-specific logic of a programmable logic device, the network receiver comprising a physical layer having a data node coupled to receive a plurality of packet assemblies from a link layer implemented in programmable logic of the programmable logic device, each packet assembly including a data frame, and a CRC generator, wherein the CRC generator is implemented in a sublayer of the physical layer separate from a physical layer interface and performs, for each packet assembly, a CRC on at least a portion of the packet assembly to provide a calculated CRC value.

32. The network receiver of claim 31, wherein each packet assembly includes a packet CRC value, the physical layer further comprising a CRC compare circuit comparing the packet CRC value to the calculated CRC value.

33. The network receiver of claim 32, wherein the link layer is connected to the CRC compare circuit.

34. The network receiver of claim 33, wherein the CRC compare circuit of the physical layer identifies mismatches between the packet CRC value and the calculated CRC value for the link layer.

35. The network receiver of claim 33, wherein the link layer rejects defective packets, and wherein the link layer relies upon the CRC compare circuit in the physical layer to identify the defective packets.

36. The network receiver of claim 31 wherein the CRC generator performs a plurality of CRC functions to support a plurality of communication standards.

37. A system, comprising:

a network; and

a transmitter coupled to the network and transmitting a plurality of data frames to the network, the transmitter comprising a physical layer implemented in hard logic and a link layer implemented using programmable logic, the link layer being coupled between the physical layer and the network, the physical layer comprising;

a data node coupled to receive a plurality of data packets, each data packet including a data frame; and

a CRC generator implemented in a sublayer of the physical layer separate from a physical layer interface and coupled to the data node to perform, for each data packet, a CRC on the data frame to provide a CRC value and to insert the CRC into the data packet.

38. The system of claim 37, wherein the link layer and the physical layer of the transmitter each comprise portions of a programmable logic device (PLD).

39. The system of claim 38, wherein the PLD is a field programmable gate array (FPGA).

40. The system of claim 37, further comprising:

a receiver coupled to the network and coupled to receive data from the network, the receiver being implemented in hard logic, the receiver having a physical layer comprising;

a data node coupled to receive a packet assembly from the network, the packet assembly including at least a portion of the data; and

a CRC generator coupled to the data node to perform a CRC on at least a portion of the packet assembly to provide a calculated CRC value.

41. The system of claim 40, wherein the link layer and the physical layer of the transmitter, and the physical layer and CRC generator of the receiver, each comprise portions of a programmable logic device (PLD).

42. The system of claim 41, wherein the PLD is a field programmable gate array (FPGA).

43. A system, comprising:

a network; and

a receiver coupled to the network to receive data from the network, the receiver being implemented in a programmable logic device, the receiver comprising;

a data node coupled to receive a plurality of packet assemblies from the network, each packet assembly including a data frame, and having a CRC generator implemented in a sublayer of the physical layer separate from a physical layer interface to perform a CRC, for each packet assembly, on at least the data frame to provide a calculated CRC value, wherein the data node and the CRC generator are implemented in hard logic; and

a link layer implemented in programmable logic of the programmable logic device.

44. The system of claim 43, wherein the physical layer and CRC generator of the receiver each comprise portions of a programmable logic device (PLD).

45. The system of claim 44, wherein the PLD is a field programmable gate array (FPGA).