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Post-layout optimization in integrated circuit design

  • US 7,111,268 B1
  • Filed: 08/20/2003
  • Issued: 09/19/2006
  • Est. Priority Date: 08/26/2002
  • Status: Active Grant
First Claim
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1. A method for placing and routing a design on an integrated circuit, said design having a plurality of objects, said method comprising:

  • (a) performing incremental placement on a routed design;

    (b) generating a new routed design using incremental routing based on results of said incremental placement;

    (c) storing said new routed design if its quality is superior to that of said routed design; and

    repeating said (a), (b), and (c) steps until a predetermined criterion is met and further comprising performing timing analysis prior to step (a) to obtain timing information and selecting a set of connections that need to be improved, wherein said incremental placement operates only on said set of connections, said set of connections selected based on deviation of said timing information from a predetermined constraint.

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