Post-layout optimization in integrated circuit design

• US 7,111,268 B1
• Filed: 08/20/2003
• Issued: 09/19/2006
• Est. Priority Date: 08/26/2002
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Verma, Vinay, Anderson, Jason H., Kalman, Sandor S.
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US10/644,132
• Time in Patent Office: 1,126 Days
• Field of Search: 716 8- 14
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method for post-layout timing optimization is disclosed. The method performs timing analysis on a design to obtain timing information such as critical paths and slack values. Incremental placement based on the timing information is performed. A new routed design is generated by applying incremental routing to the result of incremental placement. The routed design is stored if its performance is better than the previous routed design. The above steps are repeated until a predetermined criterion is met.

Claims

1. A method for placing and routing a design on an integrated circuit, said design having a plurality of objects, said method comprising:

(a) performing incremental placement on a routed design;

(b) generating a new routed design using incremental routing based on results of said incremental placement;

(c) storing said new routed design if its quality is superior to that of said routed design; and

repeating said (a), (b), and (c) steps until a predetermined criterion is met and further comprising performing timing analysis prior to step (a) to obtain timing information and selecting a set of connections that need to be improved, wherein said incremental placement operates only on said set of connections, said set of connections selected based on deviation of said timing information from a predetermined constraint.

2. The method of claim 1 wherein said incremental placement is based on said timing information.

3. The method of claim 1 wherein said incremental routing is based on said timing information.

4. The method of claim 1 wherein said quality is measured based on timing performance of said new routed design.

5. The method of claim 1 wherein said incremental placement is based on routing congestion.

6. The method of claim 1 wherein said incremental placement is based on unrouted pins in said routed design.

7. The method of claim 1 further comprising a step of selecting a set of connections that need to be improved, and said incremental placement operates only on said set of connections.

8. The method of claim 1 wherein said incremental placement uses externally supplied parameters to guide its operations.

9. The method of claim 8 wherein one of said parameters is associated with distances said objects can move.

10. The method of claim 9 wherein said distances vary with number of times said incremental placement has been performed.

11. The method of claim 8 wherein one of said parameters is associated with specifying a set of connections to consider.

12. The method of claim 8 wherein one of said parameters is associated with specifying a set of locked objects.