System and method for lithography simulation

• US 7,111,277 B2
• Filed: 11/04/2004
• Issued: 09/19/2006
• Est. Priority Date: 10/07/2003
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: Brion Technologies Incorporated (ASML Holding NV)
• Inventors: Ye, Jun, Chen, Luoqi, Chen, Xun, Lu, Yen-Wen, Cao, Yu
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US10/981,914
• Publication Number:
  US 20050097500A1
• Time in Patent Office: 684 Days
• Field of Search: 716/21, 430/5, 378/35, 700/97, 700/120, 700/121, 250/492.22
• US Class Current: 716/52
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 7/004 Photosensitive materials G03F7/12, G03F7/14 take precedence
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00

Abstract

There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.

Claims

1. A method for evaluating a design pattern on a photolithographic mask, the method comprising:

generating a pixel-based bitmap of the design pattern on the photolithographic mask using an image of the photolithographic mask;

generating a simulated image of the design pattern in wafer resist using (1) the pixel-based bitmap of the design pattern on the photolithographic mask and (2) a relationship representing an imaging path of projection and illumination optics of a photolithographic tool; and

evaluating the design pattern on the photolithographic mask by comparing the simulated image of the design pattern in wafer resist and a design target on a wafer which corresponds to the design pattern on the photolithographic mask.

2. The method of claim 1, wherein generating the simulated image of the design pattern in wafer resist further includes determining edge locations of the design pattern in wafer resist.

3. The method of claim 2, wherein generating the simulated image of the design pattern in wafer resist further includes connecting edge points of the design pattern in wafer resist.

4. The method of claim 1, wherein generating the simulated image of the design pattern in wafer resist further includes generating a three dimensional intensity distribution of the simulated image of the design pattern in wafer resist.

5. The method of claim 1, wherein generating a simulated image of the design pattern in wafer resist further includes generating a two dimensional image distribution of the simulated image of the design pattern in wafer resist.

6. The method of claim 5, wherein generating the two dimensional image distribution is representative of the simulated image of the design pattern in wafer resist at a predetermined distance from a surface of the wafer.

7. The method of claim 1, wherein the pixel-based bitmap of the design pattern on the photolithographic mask includes pixel data, wherein each pixel datum represents a pixel having a predetermined pixel size.

8. The method of claim 7, wherein the predetermined pixel size provides a sampling frequency that is greater than a Nyquist frequency in an image of the design pattern.

9. The method of claim 7, wherein the predetermined pixel size is determined using a numerical aperture and wavelength of the projection optics of the photolithographic tool.

10. The method of claim 7, wherein the design pattern on the photolithographic mask includes resolution enhancement technology.

11. The method of claim 1, wherein the relationship representing the imaging path of the projection and illumination optics is a coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic tool.

12. The method of claim 11, wherein the coefficient matrix representing the imaging path of the projection and illumination optics is representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic tool.

13. The method of claim 11, wherein the coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic tool includes transmission cross coefficients.

14. The method of claim 1, wherein generating a simulated image of the design pattern in wafer waist includes generating a simulated image of the design pattern in wafer resist using forward and backward Fast Fourier Transforms.

15. The method of claim 1, wherein the relationship representing the imaging path of the projection and illumination optics of a photolithographic tool includes formulas using a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic tool.

16. A system for evaluating a design pattern on a lithographic mask, the system comprising:

a microprocessor subsystem, including a plurality of microprocessors; and

a plurality of accelerator subsystems, each accelerator subsystem includes a plurality of programmable integrated circuits configured to process a pixel-based bitmap of the design pattern on the lithographic mask in parallel, and each accelerator subsystem is connected to an associated microprocessor to calculate a portion of a simulated image of the design pattern in wafer resist using (1) a corresponding portion of the pixel-based bitmap representation of the design pattern which is generated using an image of the lithographic mask and (2) a relationship representing an imaging path of projection and illumination optics of a photolithographic tool; and

a data processing system to compare the simulated image of the design pattern in wafer resist and a design target on a wafer which corresponds to the design pattern on the lithographic mask.

17. The system of claim 16, wherein the pixel-based bitmap uses a predetermined pixel size, and the predetermined pixel size provides a sampling frequency that is greater than a Nyquist frequency in an image of the design pattern.

18. The system of claim 16, wherein the pixel-based bitmap uses a predetermined pixel size, and wherein the predetermined pixel size is determined using a numerical aperture and wavelength of the projection optics of the photolithographic tool.

19. The system of claim 16, wherein the accelerator subsystems further perform Fast Fourier Transforms, using pixel data, to generate a corresponding portion of the simulated image of the design pattern on the lithographic mask in wafer resist.

20. The system of claim 16, wherein the relationship representing the imaging path of the projection and illumination optics includes a coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic tool.

21. The system of claim 20, wherein the coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic tool is representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic tool.

22. The system of claim 20, wherein the coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic tool are transmission cross coefficients.

23. The system of claim 16, wherein the system further determines a set of parameters representing the imaging path of the projection and illumination optics of the photolithographic tool using one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic tool.

24. The system of claim 16, wherein the plurality of accelerator subsystems further calculate a three dimensional intensity distribution of the simulated image of the design pattern in wafer resist.

25. The system of claim 16, wherein the plurality of accelerator subsystems further calculate a two dimensional image distribution of the simulated image of the design pattern in wafer resist.

26. The system of claim 25, wherein the two dimensional image distribution is representative of an image of the design pattern in wafer resist at a predetermined distance from a surface of the wafer.

27. The system of claim 16, wherein the accelerator subsystems further perform forward and backward Fast Fourier Transforms, using pixel data, to generate a corresponding portion of the simulated image of the design pattern in wafer resist.

28. A method for evaluating a design pattern on a lithographic mask, the method comprising:

generating a simulated image of the design pattern in wafer resist using (1) a pixel-based bitmap of the design pattern on the lithographic mask which is generated using an image of the lithographic mask and (2) a relationship representing an imaging path of projection and illumination optics of a photolithographic tool; and

evaluating a design pattern on a lithographic mask by comparing the simulated image of the design pattern in wafer resist and a design target on a wafer which corresponds to the design pattern on the lithographic mask.

29. The method of claim 28, wherein generating the simulated image of the design pattern in wafer resist includes determining edge locations of the design pattern in wafer resist.

30. The method of claim 29, wherein generating the simulated image of the design pattern in wafer resist includes connecting edge points of the design pattern in wafer resist.

31. The method of claim 28, wherein generating the simulated image of the design pattern in wafer resist further includes generating a three dimensional intensity distribution of the simulated image of the design pattern in wafer resist.

32. The method of claim 28, wherein generating the simulated image of the design pattern in wafer resist further includes generating a two dimensional image distribution of the simulated image of the design pattern in wafer resist at predetermined distance from a surface of a wafer.

33. The method of claim 28, wherein the design pattern on the lithographic mask includes resolution enhancement technology.

34. The method of claim 28, wherein the relationship representing the imaging path of the projection and illumination optics of a photolithographic tool includes one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic tool.

35. The method of claim 28, wherein the relationship representing the imaging path of the projection and illumination optics includes a coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic tool.

36. The method of claim 35, wherein the coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic tool includes transmission cross coefficients.

37. The method of claim 35, wherein the coefficient matrix representing the imaging path of the projection and illumination optics of the photolithographic tool is representative of one or more of a focus, dose, numerical aperture, illumination aperture, and aberration of the photolithographic tool.

38. The method of claim 28, wherein generating a simulated image of the design pattern in wafer resist includes using Fast Fourier transforms.