Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit

• US 7,112,495 B2
• Filed: 12/05/2003
• Issued: 09/26/2006
• Est. Priority Date: 08/15/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeo, Yee-Chia, Lee, Wen-Chin, Ko, Chih-Hsin, Hu, Chenming, Lin, Chun-Chieh
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US10/729,095
• Publication Number:
  US 20050035409A1
• Time in Patent Office: 1,026 Days
• Field of Search: 438/222, 438/223, 438/226, 438/227, 438/300, 438/360, 438/363, 438/429
• US Class Current: 438/300
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor chip includes a semiconductor substrate 126, in which first and second active regions are disposed. A resistor 124 is formed in the first active region and the resistor 124 includes a doped region 128 formed between two terminals 136. A strained channel transistor 132 is formed in the second active region. The transistor includes a first and second stressor 141, formed in the substrate oppositely adjacent a strained channel region 143.

Claims

1. A method of forming a semiconductor chip, the method comprising:

providing a semiconductor region comprising a first semiconductor material with a first natural lattice constant;

forming first and second active regions in the semiconductor region;

forming a first gate stack over the second active region;

forming first spacers adjacent the first gate stack;

forming a masking layer over the first active region;

after forming the masking layer, forming at least one recess in a portion of the second active region not covered by the first gate stack;

forming a second semiconductor material in the at least one recess to substantially fill the at least one recess, the second semiconductor material having a second natural lattice constant that is different than the first natural lattice constant;

forming heavily-doped source and drain regions in the second active region on opposing sides of the first gate stack;

removing the first spacers after the forming heavily-doped source and drain regions;

forming lightly-doped drains after the removing the first spacers on opposing sides of the first gate stack;

removing the masking layer; and

forming a semiconductor component in the first active region.

2. The method of claim 1 wherein the step of forming first and second active regions comprises the steps of:

forming trenches to define the active regions;

filling the trenches with a trench filling material; and

doping the active regions.

3. The method of claim 1 wherein forming the second semiconductor material comprises performing a chemical vapor deposition step.

4. The method of claim 1 wherein forming the second semiconductor material comprises performing a selective epitaxy step.

5. The method of claim 1 wherein forming a semiconductor component comprises forming a doped region in the first active region to form a resistor.

6. The method of claim 5, further comprising forming at least two electrical contacts that are electrically coupled to the doped region.

7. The method of claim 5 wherein forming the doped region comprises performing an ion implantation step.

8. The method of claim 1 wherein forming the heavily-doped source and drain regions comprises performing an ion implantation step.

9. The method of claim 1 and further comprising forming a cap layer overlying the second semiconductor material, the cap layer comprising the first semiconductor material.

10. The method of claim 1 wherein the gate stack comprises a gate electrode overlying a gate dielectric.

11. The method of claim 10 wherein the gate stack further comprises a gate mask overlying the gate electrode.

12. The method of claim 1 wherein the second natural lattice constant is larger than the first natural lattice constant.

13. The method of claim 1 wherein the first semiconductor material comprises silicon and the second semiconductor material comprises silicon and germanium.

14. The method of claim 13 wherein forming heavily-doped source and drain regions comprises P-typed doped regions.

15. The method of claim 1 wherein the second natural lattice constant is smaller than the first natural lattice constant.

16. The method of claim 1 wherein the first semiconductor material is silicon and the second semiconductor material comprises silicon and carbon.

17. The method of claim 1 further comprising a step of forming silicide on the gate stack, the source region, and the drain region.

18. The method of claim 1 further comprising steps of:

forming contact etch stop layer over the resistor and the semiconductor component;

forming passivation layer over the contact etch stop layer; and

forming contacts to the resistor and transistor through the contact etch stop layer.

19. The method of claim 1 wherein the semiconductor component comprises a transistor.

20. The method of claim 19 wherein the transistor comprises a strained channel field effect transistor.

21. The method of claim 19 wherein the strained channel transistor comprises a transistor of first doping type and wherein the semiconductor component comprises a transistor of a second doping type.

22. The method of claim 19 wherein the forming to first spacers comprises:

forming a disposable film over the second active region, the disposable film overlying the gate stack; and

processing the disposable film to form disposable spacers on sidewalls of the gate stack in the second active region;

wherein the at least one recess is formed adjacent a disposable spacer.

23. The method of claim 19 and further comprising forming a second gate stack over the first active region, wherein the first gate stack and second gate stack each comprises a gate electrode overlying a gate dielectric.

24. The method of claim 1 and further comprising forming second spacers onto sidewalls of the first gate stack.

25. The method of claim 1 and further comprising forming a hard mask over the first gate stack and first spacers.

26. The method of claim 25 wherein the hard mask comprises multiple layers of material.

27. The method of claim 25 and further comprising, after growing to second semiconductor material, removing the hard mask.

28. The method of claim 1 wherein the second semiconductor material is in-situ doped with a p-type dopant.

29. The method of claim 28 wherein the second semiconductor material is in-situ doped with a dopant selected from the group consisting of boron, indium, and combinations thereof.

30. The method of claim 1 wherein the second semiconductor material is in-situ doped with an n-type dopant.

31. The method of claim 30 wherein the second semiconductor material is in-situ doped with a dopant selected from the group consisting of As, P, Sb, and combinations thereof.

32. The method of claim 1 and further comprising, after forming the heavily-doped source and drain regions, forming a first conductive material on the heavily-doped source and drain regions.

33. The method of claim 32 wherein the first conductive material comprises cobalt germanosilicide Co(SiGe), nickel germanosilicide Ni(SiGe), Co(SiC), or Ni(SiC), or combinations thereof.

34. A method of forming a semiconductor device, the method comprising:

providing a semiconductor substrate comprising a first semiconductor material, the substrate including a first active region and a second active region, the first active region having a first gate stack formed thereon and the second active region having a second gate stack farmed thereon;

forming a film over first active region and second active region;

forming spacers on sidewalls of the second gate stack in the second active region;

etching a source recess and a drain recess on opposing sides of the second gate stack, the source recess and the drain recess spaced from a channel region by the spacers;

growing a second semiconductor material in the source recess and the drain recess;

forming heavily-doped regions on opposing sides of the second gate stack;

removing the spacers after forming the heavily-doped regions; and

forming lightly-doped regions on opposing sides of the second gate stack after removing the spacers.

35. The method of claim 34 wherein the first gate stack and second gate stack each comprise a gate electrode overlying a gate dielectric.

36. The method of claim 35 further comprising a hard mask overlying the gate electrode.

37. The method of claim 36 wherein the hard mask comprises multiple layers of hard mask material.

38. The method of claim 36 wherein the hard mask comprises silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

39. The method of claim 36 and further comprising, after growing the second semiconductor material, removing the hard mask.

40. The method of claim 34 wherein the first semiconductor material comprises silicon.

41. The method of claim 40 wherein the second semiconductor material comprises silicon and germanium.

42. The method of claim 40 wherein the second semiconductor material comprises silicon and carbon.

43. The method of claim 34 wherein the semiconductor substrate comprises an insulator layer underlying the first semiconductor material.

44. The method of claim 34 wherein the semiconductor substrate comprises a relaxed SiGe layer underlying the first semiconductor material.

45. The method of claim 44 wherein the first semiconductor material comprises silicon.

46. The method of claim 34 wherein the second semiconductor material is in-situ doped with a p-type dopant.

47. The method of claim 46 wherein the p-type dopant is selected from the group consisting of boron, indium, and combinations thereof.

48. The method of claim 34 wherein the second semiconductor material is in-situ doped with an n-type dopant.

49. The method of claim 48 wherein the n-type dopant is selected from the group consisting of As, P, Sb, and combinations thereof.

50. The method of claim 34 and further comprising:

forming a first source region and a first drain region in the first active region oppositely adjacent to the first gate stack.

51. The method of claim 50 and further comprising, after forming the first source region and the first drain region, forming a first conductive material on the first source region and the first drain region.

52. The method of claim 51 wherein the first conductive material comprises cobalt silicide CoSi, nickel silicide NiSi, cobalt germanosilicide Co(SiGe), nickel germanosilicide Ni(SiGe), Co(SiC), Ni(SiC) or combinations thereof.

53. The method of claim 50 and further comprising, after forming the lightly-doped regions, forming a second conductive material on the lightly-doped regions.

54. The method of claim 53 wherein the second conductive material comprises cobalt suicide CoSi, nickel suicide NiSi, cobaltgermanosilicide Co(SiGe), nickelgermauosilicide Ni(SiGe), Co(SiC), Ni(SiC) or combinations thereof.

55. The method of claim 34 wherein forming spacers on sidewalls of the second gate stack comprises:

forming a disposable film over the second active region including the second gate stack; and

forming disposable spacers by etching the disposable film.

56. The method of claim 55 wherein the step of forming a film over the first active region and the second active region comprises the step of forming a disposable film, the method further comprising forming a masking layer over a portion of the disposable film overlying the first active region prior to forming disposable spacers.

57. The method of claim 55 wherein forming disposable spacers comprises performing a plasma etch process or a wet etch process.

58. The method of claim 55 and further comprising removing the disposable spacers after forming the source recess and the drain recess.

59. The method of claim 58 and further comprising, after growing the second semiconductor material, forming spacers on sidewalls of the first gate stack and the second gate stack.

60. The method of claim 59 wherein the spacers on the sides of first and second gate stacks are composite spacers.

61. The method of claim 34 wherein growing a second semiconductor material comprises a performing selective epitaxy process.

62. The method of claim 34 and further comprising, after growing a second semiconductor material, selectively growing a first semiconductor material overlying the second semiconductor material.

63. The method of claim 34 wherein the first gate stack and the second gate stack each include a gate electrode formed from a material selected from the group consisting of polycrystalline silicon, polycrystalline silicon-germanium, a metal, a metal suicide, a metal nitride, and combinations thereof.

64. The method of claim 34 wherein the first gate stack and the second gate stank each include a gate dielectric formed from a material selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, or combinations thereof.

65. A method of forming a semiconductor device, the method comprising;

providing a semiconductor layer that includes a first active region and a second active region;

forming a first gate stack over the first active region and a second gate stack over the second active region;

forming a dielectric film over the first active region and the second active region;

forming a masking layer over a portion of the dielectric film overlying the second active region;

forming disposable spacers on sidewalls of the first gate stack by anisotropically etching the dielectric film;

forming first and second recesses in the first active region substantially aligned with the disposable spacer;

filling the first and second recesses with a semiconductor material;

implanting source and drain regions in the second active region adjacent the second gate stack;

removing the disposable spacers; and

forming lightly-doped drains on opposing sides of the first gate stack after removing the disposable spacers.

66. The method of claim 65 and further comprising, after filling the first and second recesses, removing the dielectric film over the first active region.

67. The method of claim 66 and, after removing the disposable spacers and the dielectric film, further comprising:

forming lightly doped regions of a first conductivity type in the first active region adjacent the first gate stack;

forming lightly doped regions of a second conductivity type in the second active region adjacent the second gate stack;

forming first spacers adjacent the first gate stack and second spacers adjacent the second stack;

forming heavily doped regions of the first conductivity type in the first active region adjacent the first spacers; and

forming heavily doped regions of the second conductivity type in the first active region adjacent the first gate stack.

68. The method of claim 65 and, after filling the first and second recesses, further comprising:

removing the masking layer from over the second active region;

forming a second masking layer over the first active region; and

etching the second masking layer over the second active region to form second spacers adjacent the second gate stack.

69. The method of claim 68 wherein implanting a source region and a drain region comprises implanting a source region and a drain region in the second active region aligned with the second spacers.

70. The method of claim 69 and further comprising, after implanting the source region and the drain region, removing the disposable spacers and the second spacers.

71. The method of claim 70 and further comprising, after removing the disposable spacers and the second spacers, forming a first lightly doped region in the first active region adjacent the first gate stack and forming a second lightly doped region in the second active region adjacent the second gate stack.