Thin channel MOSFET with source/drain stressors
First Claim
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1. A microelectronic device, comprising:
- a silicon-on-insulator substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer;
a pedestal having a first width defined from the thin semiconductor and insulating layers over the bulk semiconductor portion, wherein the portion of the pedestal defined from the thin semiconductor layer comprises a channel region interposing source/drain extensions;
a gate electrode having a second width and located over the pedestal, wherein the second width is different than the first width; and
source/drain stressors located over the bulk semiconductor portion and each contacting a corresponding one of the source/drain extensions, wherein at least one of the source/drain stressors is thicker than the channel region.
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Abstract
Methods of manufacturing microelectronic device including, in one embodiment, forming a gate electrode over a substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer, and removing at least a portion of the thin semiconductor and insulating layers, thereby defining a pedestal comprising a portion of the thin semiconductor and insulating layers. Source/drain stressors are then formed contacting the source/drain extensions on opposing sides of the pedestal and substantially spanning a height no less than the pedestal.
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Citations
17 Claims
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1. A microelectronic device, comprising:
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a silicon-on-insulator substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer; a pedestal having a first width defined from the thin semiconductor and insulating layers over the bulk semiconductor portion, wherein the portion of the pedestal defined from the thin semiconductor layer comprises a channel region interposing source/drain extensions; a gate electrode having a second width and located over the pedestal, wherein the second width is different than the first width; and source/drain stressors located over the bulk semiconductor portion and each contacting a corresponding one of the source/drain extensions, wherein at least one of the source/drain stressors is thicker than the channel region. - View Dependent Claims (2, 3, 4)
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5. An integrated circuit device, comprising:
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a plurality of microelectronic devices located at least partially in a substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer, wherein ones of the plurality of microelectronic devices comprise; a pedestal having a first width defined from the thin semiconductor and insulating layers over the bulk semiconductor portion, wherein the portion of the pedestal defined from the thin semiconductor layer comprises a channel region interposing source/drain extensions; a gate electrode having a second width and located over the pedestal, wherein the second width is different from the first width; and source/drain stressors located over the bulk semiconductor portion and each contacting a corresponding one of the source/drain extensions, wherein at least one of the source/drain stressors is thicker than the channel region; and a plurality of interconnects interconnecting ones of the plurality of microelectronic devices. - View Dependent Claims (6, 7, 8, 9)
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10. A microelectronic device, comprising:
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a silicon-on-insulator substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer; a pedestal having a first width defined from the thin semiconductor layer and the insulating layer, wherein the portion of the pedestal defined from the thin semiconductor layer comprises source/drain extensions and a channel region interposing the source/drain extensions; a gate electrode having a second width and located over the pedestal, wherein the second width is substantially less than the first width; source/drain stressors located over the bulk semiconductor portion, wherein the source/drain stressors each span the insulating layer portion of the pedestal and contact a corresponding one of the source/drain extensions; and doped regions formed in the bulk semiconductor portion of the silicon-on-insulator substrate thus separating the remainder of the bulk semiconductor portion from the source/drain stressors; wherein the source/drain stressors each have a first lattice structure that is different relative to at least one of a second lattice structure of the source/drain extensions and a third lattice structure of the doped regions formed in the bulk semiconductor portion of the silicon-on-insulator substrate. - View Dependent Claims (11, 12, 13)
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14. A microelectronic device, comprising:
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a silicon-on-insulator substrate having an insulating layer interposing a bulk semiconductor portion and a thin semiconductor layer; a pedestal defined from the thin semiconductor and insulating layers, wherein the portion of the pedestal defined from the thin semiconductor layer comprises a source extension, a drain extension, and a channel region interposing the source and drain extensions; a gate electrode located over the pedestal, wherein the gate electrode is greater in width relative to a substantial portion of the pedestal; and a source stressor and a drain stressor located on opposing sides of the pedestal and each contacting a corresponding one of the source and drain extensions, wherein at least one of the source and drain stressors is thicker than the channel region. - View Dependent Claims (15, 16, 17)
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Specification