Semiconductor device

• US 7,112,881 B2
• Filed: 09/22/2004
• Issued: 09/26/2006
• Est. Priority Date: 09/24/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Noma, Takashi, Kaida, Takayuki, Shimizu, Ryu, Miwa, Tetsuya, Okigawa, Mitsuru
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US10/945,945
• Publication Number:
  US 20050062146A1
• Time in Patent Office: 734 Days
• Field of Search: 257698-699, 257/621, 257/708, 257773-774
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A semiconductor device allowing simplification of a fabrication process is provided. This semiconductor device comprises a first insulator film, consisting of a single material, formed to be in contact with the upper surface of a semiconductor chip including a circuit, a first wire formed to be in contact with the upper surface of the first insulator film and a second wire formed to extend along the side surface and the lower surface of the semiconductor chip and connected to the lower surface of the first wire exposed by partially removing the first insulator film.

Claims

1. A semiconductor device comprising:

a first insulator film, consisting of a single material, formed to be in contact with the upper surface of a semiconductor chip including a circuit;

a first wire formed to be in contact with the upper surface of said first insulator film;

a second wire formed to extend along the side surface and the lower surface of said semiconductor chip and connected to the lower surface of said first wire exposed by partially removing said first insulator film; and

a third insulator film, provided between said semiconductor chip and said second wire to isolate said semiconductor chip and said second wire from each other and formed to cover a prescribed region of the lower surface of said first insulator film, consisting of a material removable by etching means substantially identical to that for said first insulator film.

2. The semiconductor device according to claim 1, wherein said etching means includes an etching solution employed for wet etching.

3. The semiconductor device according to claim 1, wherein said third insulator film consists of the same material as said first insulator film.